make: Entering directory '/home/dsleung/Desktop/riscv-formal/cores/picorv32/checks' sby reg_ch0.sby sby causal_ch0.sby sby cover.sby sby csrw_mcycle_ch0.sby sby csrw_minstret_ch0.sby sby liveness_ch0.sby sby pc_bwd_ch0.sby sby pc_fwd_ch0.sby sby unique_ch0.sby sby insn_add_ch0.sby sby insn_addi_ch0.sby sby insn_and_ch0.sby sby insn_andi_ch0.sby sby insn_auipc_ch0.sby sby insn_beq_ch0.sby sby insn_bge_ch0.sby SBY 16:39:00 [pc_bwd_ch0] Writing 'pc_bwd_ch0/src/defines.sv'. SBY 16:39:00 [causal_ch0] Writing 'causal_ch0/src/defines.sv'. SBY 16:39:00 [pc_bwd_ch0] Writing 'pc_bwd_ch0/src/pc_bwd_ch0.sv'. SBY 16:39:00 [csrw_mcycle_ch0] Writing 'csrw_mcycle_ch0/src/defines.sv'. SBY 16:39:00 [causal_ch0] Writing 'causal_ch0/src/causal_ch0.sv'. SBY 16:39:00 [pc_bwd_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'pc_bwd_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [csrw_mcycle_ch0] Writing 'csrw_mcycle_ch0/src/csrw_mcycle_ch0.sv'. SBY 16:39:00 [causal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'causal_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [csrw_mcycle_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'csrw_mcycle_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [pc_bwd_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'pc_bwd_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [causal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'causal_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [csrw_mcycle_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'csrw_mcycle_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [pc_bwd_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'pc_bwd_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [causal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'causal_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [reg_ch0] Writing 'reg_ch0/src/defines.sv'. SBY 16:39:00 [csrw_minstret_ch0] Writing 'csrw_minstret_ch0/src/defines.sv'. SBY 16:39:00 [csrw_mcycle_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'csrw_mcycle_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [pc_bwd_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_pc_bwd_check.sv' to 'pc_bwd_ch0/src/rvfi_pc_bwd_check.sv'. SBY 16:39:00 [reg_ch0] Writing 'reg_ch0/src/reg_ch0.sv'. SBY 16:39:00 [causal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_causal_check.sv' to 'causal_ch0/src/rvfi_causal_check.sv'. SBY 16:39:00 [pc_fwd_ch0] Writing 'pc_fwd_ch0/src/defines.sv'. SBY 16:39:00 [csrw_minstret_ch0] Writing 'csrw_minstret_ch0/src/csrw_minstret_ch0.sv'. SBY 16:39:00 [csrw_mcycle_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_csrw_check.sv' to 'csrw_mcycle_ch0/src/rvfi_csrw_check.sv'. SBY 16:39:00 [reg_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'reg_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [pc_fwd_ch0] Writing 'pc_fwd_ch0/src/pc_fwd_ch0.sv'. SBY 16:39:00 [csrw_minstret_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'csrw_minstret_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [unique_ch0] Writing 'unique_ch0/src/defines.sv'. SBY 16:39:00 [cover] Writing 'cover/src/defines.sv'. SBY 16:39:00 [pc_fwd_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'pc_fwd_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [unique_ch0] Writing 'unique_ch0/src/unique_ch0.sv'. SBY 16:39:00 [reg_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'reg_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [cover] Writing 'cover/src/cover.sv'. SBY 16:39:00 [csrw_minstret_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'csrw_minstret_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [unique_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'unique_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [cover] Writing 'cover/src/cover_stmts.vh'. SBY 16:39:00 [reg_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'reg_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [pc_fwd_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'pc_fwd_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [csrw_minstret_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'csrw_minstret_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [cover] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'cover/src/rvfi_macros.vh'. SBY 16:39:00 [reg_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_reg_check.sv' to 'reg_ch0/src/rvfi_reg_check.sv'. SBY 16:39:00 [unique_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'unique_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [pc_fwd_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'pc_fwd_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [liveness_ch0] Writing 'liveness_ch0/src/defines.sv'. SBY 16:39:00 [insn_beq_ch0] Writing 'insn_beq_ch0/src/defines.sv'. SBY 16:39:00 [csrw_minstret_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_csrw_check.sv' to 'csrw_minstret_ch0/src/rvfi_csrw_check.sv'. SBY 16:39:00 [insn_addi_ch0] Writing 'insn_addi_ch0/src/defines.sv'. SBY 16:39:00 [cover] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'cover/src/rvfi_channel.sv'. SBY 16:39:00 [liveness_ch0] Writing 'liveness_ch0/src/liveness_ch0.sv'. SBY 16:39:00 [unique_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'unique_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [insn_beq_ch0] Writing 'insn_beq_ch0/src/insn_beq_ch0.sv'. SBY 16:39:00 [pc_fwd_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_pc_fwd_check.sv' to 'pc_fwd_ch0/src/rvfi_pc_fwd_check.sv'. SBY 16:39:00 [insn_addi_ch0] Writing 'insn_addi_ch0/src/insn_addi_ch0.sv'. SBY 16:39:00 [liveness_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'liveness_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [insn_add_ch0] Writing 'insn_add_ch0/src/defines.sv'. SBY 16:39:00 [insn_beq_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_beq_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [cover] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'cover/src/rvfi_testbench.sv'. SBY 16:39:00 [unique_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_unique_check.sv' to 'unique_ch0/src/rvfi_unique_check.sv'. SBY 16:39:00 [insn_and_ch0] Writing 'insn_and_ch0/src/defines.sv'. SBY 16:39:00 [insn_andi_ch0] Writing 'insn_andi_ch0/src/defines.sv'. SBY 16:39:00 [insn_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_addi_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [insn_auipc_ch0] Writing 'insn_auipc_ch0/src/defines.sv'. SBY 16:39:00 [insn_add_ch0] Writing 'insn_add_ch0/src/insn_add_ch0.sv'. SBY 16:39:00 [insn_and_ch0] Writing 'insn_and_ch0/src/insn_and_ch0.sv'. SBY 16:39:00 [insn_andi_ch0] Writing 'insn_andi_ch0/src/insn_andi_ch0.sv'. SBY 16:39:00 [cover] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_cover_check.sv' to 'cover/src/rvfi_cover_check.sv'. SBY 16:39:00 [insn_beq_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_beq_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [liveness_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'liveness_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [insn_auipc_ch0] Writing 'insn_auipc_ch0/src/insn_auipc_ch0.sv'. SBY 16:39:00 [insn_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_add_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [insn_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_addi_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [insn_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_and_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [insn_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_andi_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [insn_auipc_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_auipc_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [insn_beq_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_beq_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [liveness_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'liveness_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [insn_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_addi_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [insn_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_add_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [insn_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_and_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [insn_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_andi_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [insn_beq_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_beq_ch0/src/rvfi_insn_check.sv'. SBY 16:39:00 [insn_auipc_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_auipc_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [liveness_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_liveness_check.sv' to 'liveness_ch0/src/rvfi_liveness_check.sv'. SBY 16:39:00 [insn_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_addi_ch0/src/rvfi_insn_check.sv'. SBY 16:39:00 [insn_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_add_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [insn_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_andi_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [insn_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_and_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [insn_beq_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_beq.v' to 'insn_beq_ch0/src/insn_beq.v'. SBY 16:39:00 [insn_auipc_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_auipc_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [insn_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_addi.v' to 'insn_addi_ch0/src/insn_addi.v'. SBY 16:39:00 [insn_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_add_ch0/src/rvfi_insn_check.sv'. SBY 16:39:00 [causal_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [pc_bwd_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_andi_ch0/src/rvfi_insn_check.sv'. SBY 16:39:00 [insn_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_and_ch0/src/rvfi_insn_check.sv'. SBY 16:39:00 [insn_auipc_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_auipc_ch0/src/rvfi_insn_check.sv'. SBY 16:39:00 [csrw_mcycle_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_add.v' to 'insn_add_ch0/src/insn_add.v'. SBY 16:39:00 [insn_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_andi.v' to 'insn_andi_ch0/src/insn_andi.v'. SBY 16:39:00 [insn_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_and.v' to 'insn_and_ch0/src/insn_and.v'. SBY 16:39:00 [insn_auipc_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_auipc.v' to 'insn_auipc_ch0/src/insn_auipc.v'. SBY 16:39:00 [insn_bge_ch0] Writing 'insn_bge_ch0/src/defines.sv'. SBY 16:39:00 [insn_bge_ch0] Writing 'insn_bge_ch0/src/insn_bge_ch0.sv'. SBY 16:39:00 [insn_bge_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_bge_ch0/src/rvfi_macros.vh'. SBY 16:39:00 [reg_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [csrw_minstret_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_bge_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_bge_ch0/src/rvfi_channel.sv'. SBY 16:39:00 [pc_fwd_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [unique_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_bge_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_bge_ch0/src/rvfi_testbench.sv'. SBY 16:39:00 [cover] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_bge_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_bge_ch0/src/rvfi_insn_check.sv'. SBY 16:39:00 [insn_bge_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_bge.v' to 'insn_bge_ch0/src/insn_bge.v'. SBY 16:39:00 [liveness_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_beq_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_addi_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_add_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_andi_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_and_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_auipc_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [insn_bge_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:00 [pc_bwd_ch0] base: starting process "cd pc_bwd_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [causal_ch0] base: starting process "cd causal_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [csrw_mcycle_ch0] base: starting process "cd csrw_mcycle_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [csrw_minstret_ch0] base: starting process "cd csrw_minstret_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [reg_ch0] base: starting process "cd reg_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [unique_ch0] base: starting process "cd unique_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [pc_fwd_ch0] base: starting process "cd pc_fwd_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [cover] base: starting process "cd cover/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [insn_beq_ch0] base: starting process "cd insn_beq_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [insn_addi_ch0] base: starting process "cd insn_addi_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [liveness_ch0] base: starting process "cd liveness_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [insn_add_ch0] base: starting process "cd insn_add_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [insn_andi_ch0] base: starting process "cd insn_andi_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [insn_auipc_ch0] base: starting process "cd insn_auipc_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [insn_and_ch0] base: starting process "cd insn_and_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:00 [insn_bge_ch0] base: starting process "cd insn_bge_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:04 [cover] base: finished (returncode=0) SBY 16:39:04 [cover] smt2: starting process "cd cover/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [unique_ch0] base: finished (returncode=0) SBY 16:39:04 [unique_ch0] smt2: starting process "cd unique_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [insn_auipc_ch0] base: finished (returncode=0) SBY 16:39:04 [insn_auipc_ch0] smt2: starting process "cd insn_auipc_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [liveness_ch0] base: finished (returncode=0) SBY 16:39:04 [liveness_ch0] smt2: starting process "cd liveness_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [cover] smt2: finished (returncode=0) SBY 16:39:04 [cover] engine_0: starting process "cd cover; yosys-smtbmc -s boolector --unroll -c --noprogress -t 15:16 --append 0 --dump-vcd engine_0/trace%.vcd --dump-vlogtb engine_0/trace%_tb.v --dump-smtc engine_0/trace%.smtc model/design_smt2.smt2" SBY 16:39:04 [pc_fwd_ch0] base: finished (returncode=0) SBY 16:39:04 [pc_fwd_ch0] smt2: starting process "cd pc_fwd_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [insn_andi_ch0] base: finished (returncode=0) SBY 16:39:04 [insn_andi_ch0] smt2: starting process "cd insn_andi_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [reg_ch0] base: finished (returncode=0) SBY 16:39:04 [reg_ch0] smt2: starting process "cd reg_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [causal_ch0] base: finished (returncode=0) SBY 16:39:04 [causal_ch0] smt2: starting process "cd causal_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [cover] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [unique_ch0] smt2: finished (returncode=0) SBY 16:39:04 [unique_ch0] engine_0: starting process "cd unique_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 30:31 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [pc_bwd_ch0] base: finished (returncode=0) SBY 16:39:04 [pc_bwd_ch0] smt2: starting process "cd pc_bwd_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [insn_and_ch0] base: finished (returncode=0) SBY 16:39:04 [insn_and_ch0] smt2: starting process "cd insn_and_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [insn_bge_ch0] base: finished (returncode=0) SBY 16:39:04 [insn_bge_ch0] smt2: starting process "cd insn_bge_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [insn_beq_ch0] base: finished (returncode=0) SBY 16:39:04 [insn_beq_ch0] smt2: starting process "cd insn_beq_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [insn_auipc_ch0] smt2: finished (returncode=0) SBY 16:39:04 [insn_auipc_ch0] engine_0: starting process "cd insn_auipc_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [insn_addi_ch0] base: finished (returncode=0) SBY 16:39:04 [insn_addi_ch0] smt2: starting process "cd insn_addi_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [unique_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [liveness_ch0] smt2: finished (returncode=0) SBY 16:39:04 [liveness_ch0] engine_0: starting process "cd liveness_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 30:31 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [insn_add_ch0] base: finished (returncode=0) SBY 16:39:04 [insn_add_ch0] smt2: starting process "cd insn_add_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [pc_fwd_ch0] smt2: finished (returncode=0) SBY 16:39:04 [pc_fwd_ch0] engine_0: starting process "cd pc_fwd_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 30:31 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [reg_ch0] smt2: finished (returncode=0) SBY 16:39:04 [reg_ch0] engine_0: starting process "cd reg_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 25:26 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [insn_andi_ch0] smt2: finished (returncode=0) SBY 16:39:04 [insn_andi_ch0] engine_0: starting process "cd insn_andi_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [insn_auipc_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [liveness_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [csrw_mcycle_ch0] base: finished (returncode=0) SBY 16:39:04 [csrw_mcycle_ch0] smt2: starting process "cd csrw_mcycle_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [causal_ch0] smt2: finished (returncode=0) SBY 16:39:04 [causal_ch0] engine_0: starting process "cd causal_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 30:31 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [csrw_minstret_ch0] base: finished (returncode=0) SBY 16:39:04 [csrw_minstret_ch0] smt2: starting process "cd csrw_minstret_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:04 [pc_fwd_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [pc_bwd_ch0] smt2: finished (returncode=0) SBY 16:39:04 [pc_bwd_ch0] engine_0: starting process "cd pc_bwd_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 30:31 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 0.. SBY 16:39:04 [reg_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [insn_andi_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [insn_and_ch0] smt2: finished (returncode=0) SBY 16:39:04 [insn_and_ch0] engine_0: starting process "cd insn_and_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [insn_bge_ch0] smt2: finished (returncode=0) SBY 16:39:04 [insn_bge_ch0] engine_0: starting process "cd insn_bge_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [causal_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [insn_beq_ch0] smt2: finished (returncode=0) SBY 16:39:04 [insn_beq_ch0] engine_0: starting process "cd insn_beq_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [pc_bwd_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [insn_addi_ch0] smt2: finished (returncode=0) SBY 16:39:04 [insn_addi_ch0] engine_0: starting process "cd insn_addi_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [unique_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:04 [insn_and_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [insn_add_ch0] smt2: finished (returncode=0) SBY 16:39:04 [insn_add_ch0] engine_0: starting process "cd insn_add_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [insn_bge_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [insn_beq_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [insn_addi_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [insn_add_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [liveness_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:04 [insn_auipc_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:04 [csrw_mcycle_ch0] smt2: finished (returncode=0) SBY 16:39:04 [csrw_mcycle_ch0] engine_0: starting process "cd csrw_mcycle_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 30:31 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [csrw_minstret_ch0] smt2: finished (returncode=0) SBY 16:39:04 [csrw_minstret_ch0] engine_0: starting process "cd csrw_minstret_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 30:31 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:04 [pc_fwd_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:04 [reg_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:04 [insn_andi_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:04 [csrw_mcycle_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [causal_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:04 [csrw_minstret_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:04 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 1.. SBY 16:39:04 [unique_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:04 [pc_bwd_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:05 [insn_and_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:05 [insn_bge_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:05 [insn_beq_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:05 [liveness_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [insn_auipc_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [insn_addi_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:05 [insn_add_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:05 [pc_fwd_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [reg_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [insn_andi_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [causal_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [unique_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [pc_bwd_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [csrw_mcycle_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:05 [csrw_minstret_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:05 [insn_and_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [insn_bge_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [insn_auipc_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 2.. SBY 16:39:05 [liveness_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [insn_beq_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [insn_addi_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [pc_fwd_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [insn_add_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [reg_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [insn_andi_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [causal_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [unique_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [pc_bwd_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [csrw_mcycle_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [insn_and_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [csrw_minstret_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:05 [insn_bge_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [insn_auipc_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [liveness_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [insn_beq_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [insn_addi_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [pc_fwd_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [insn_add_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [reg_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [insn_andi_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [causal_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 3.. SBY 16:39:05 [unique_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [pc_bwd_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [csrw_mcycle_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [insn_and_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [csrw_minstret_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:05 [insn_auipc_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [insn_bge_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [insn_beq_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [liveness_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [insn_addi_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [insn_add_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [pc_fwd_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [reg_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [insn_andi_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [causal_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [unique_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [pc_bwd_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [csrw_mcycle_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [insn_and_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [csrw_minstret_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:05 [insn_auipc_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [insn_bge_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [insn_beq_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [liveness_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [insn_addi_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [pc_fwd_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [insn_add_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 4.. SBY 16:39:05 [reg_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [insn_andi_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [causal_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [unique_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [pc_bwd_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [csrw_mcycle_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [insn_and_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [csrw_minstret_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:05 [insn_auipc_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [insn_bge_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [insn_beq_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [liveness_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [insn_add_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [insn_addi_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [pc_fwd_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [reg_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [insn_andi_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [causal_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [unique_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:05 [pc_bwd_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [csrw_mcycle_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [insn_and_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [csrw_minstret_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:05 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 5.. SBY 16:39:05 [insn_auipc_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:05 [insn_bge_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [insn_beq_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [liveness_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:05 [insn_add_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [insn_addi_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:05 [pc_fwd_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:05 [insn_andi_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:05 [reg_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [causal_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [unique_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [pc_bwd_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [insn_and_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [csrw_mcycle_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:06 [csrw_minstret_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:06 [insn_auipc_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [insn_beq_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [insn_bge_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [liveness_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [insn_add_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [insn_addi_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [pc_fwd_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [insn_andi_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [reg_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [causal_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 6.. SBY 16:39:06 [unique_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [pc_bwd_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [insn_and_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [csrw_mcycle_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [csrw_minstret_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:06 [insn_auipc_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [insn_beq_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [insn_bge_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [insn_add_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [liveness_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [insn_addi_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [pc_fwd_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [insn_andi_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [reg_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [causal_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [unique_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [pc_bwd_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [insn_and_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [csrw_mcycle_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [csrw_minstret_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:06 [insn_auipc_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [insn_beq_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [insn_bge_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [insn_add_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [liveness_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [pc_fwd_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [insn_addi_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [insn_andi_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [reg_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 7.. SBY 16:39:06 [causal_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [unique_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [pc_bwd_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [insn_and_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [csrw_mcycle_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [csrw_minstret_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:06 [insn_auipc_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [insn_beq_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [insn_bge_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [insn_add_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [liveness_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [pc_fwd_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [insn_addi_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [insn_andi_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [reg_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [causal_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [unique_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [insn_and_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [pc_bwd_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [csrw_mcycle_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [insn_auipc_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [csrw_minstret_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:06 [insn_beq_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [insn_add_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [insn_bge_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [insn_addi_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [liveness_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [pc_fwd_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [insn_andi_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [reg_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [causal_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [insn_and_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [unique_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [pc_bwd_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [csrw_mcycle_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [csrw_minstret_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:06 [insn_auipc_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [insn_beq_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [insn_add_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [insn_bge_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [insn_addi_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [liveness_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [pc_fwd_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [insn_andi_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [reg_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [causal_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [insn_and_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [unique_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:06 [pc_bwd_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [csrw_mcycle_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [insn_auipc_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:06 [csrw_minstret_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:06 [insn_add_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [insn_beq_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [insn_bge_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [pc_fwd_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:06 [liveness_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:06 [insn_addi_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:06 [insn_andi_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [reg_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [causal_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [insn_and_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [pc_bwd_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [unique_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [csrw_mcycle_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:07 [insn_add_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [insn_auipc_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [csrw_minstret_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:07 [insn_beq_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [insn_bge_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [pc_fwd_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [liveness_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [insn_addi_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [insn_andi_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [reg_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [insn_and_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [causal_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [pc_bwd_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [unique_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [insn_add_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [csrw_mcycle_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [insn_auipc_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [csrw_minstret_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:07 [insn_beq_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [insn_bge_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [pc_fwd_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [insn_addi_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [insn_andi_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [liveness_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [reg_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [insn_and_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [causal_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [pc_bwd_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 8.. SBY 16:39:07 [insn_add_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [unique_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [csrw_mcycle_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [insn_auipc_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [csrw_minstret_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:07 [insn_beq_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [insn_bge_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [insn_addi_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [pc_fwd_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [insn_andi_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [liveness_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [reg_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [insn_and_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [causal_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [pc_bwd_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [unique_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [insn_add_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [csrw_mcycle_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [insn_auipc_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [insn_beq_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [csrw_minstret_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:07 [insn_bge_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [pc_fwd_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [insn_andi_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [insn_addi_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [liveness_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [reg_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 9.. SBY 16:39:07 [insn_and_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [pc_bwd_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [causal_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [insn_add_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [unique_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:07 [insn_auipc_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:07 [csrw_mcycle_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [insn_beq_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [csrw_minstret_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:07 [insn_bge_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [pc_fwd_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:07 [insn_andi_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:07 [insn_addi_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [liveness_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:07 [reg_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:07 [insn_and_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:07 [insn_add_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:07 [pc_bwd_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:07 [causal_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:07 [unique_ch0] engine_0: ## 0:00:03 Skipping step 20.. SBY 16:39:07 [csrw_mcycle_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [insn_auipc_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:07 [insn_beq_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:07 [csrw_minstret_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:07 [insn_bge_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:07 [insn_andi_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:07 [pc_fwd_ch0] engine_0: ## 0:00:03 Skipping step 20.. SBY 16:39:07 [insn_addi_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:07 [liveness_ch0] engine_0: ## 0:00:03 Skipping step 20.. SBY 16:39:07 [reg_ch0] engine_0: ## 0:00:03 Skipping step 20.. SBY 16:39:07 [insn_and_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:07 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 10.. SBY 16:39:07 [insn_add_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:07 [pc_bwd_ch0] engine_0: ## 0:00:03 Skipping step 20.. SBY 16:39:07 [causal_ch0] engine_0: ## 0:00:03 Skipping step 20.. SBY 16:39:07 [unique_ch0] engine_0: ## 0:00:03 Skipping step 21.. SBY 16:39:07 [csrw_mcycle_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:07 [insn_beq_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:07 [csrw_minstret_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:08 [insn_bge_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:08 [pc_fwd_ch0] engine_0: ## 0:00:03 Skipping step 21.. SBY 16:39:08 [insn_addi_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:08 [liveness_ch0] engine_0: ## 0:00:03 Skipping step 21.. SBY 16:39:08 [reg_ch0] engine_0: ## 0:00:03 Skipping step 21.. SBY 16:39:08 [pc_bwd_ch0] engine_0: ## 0:00:03 Skipping step 21.. SBY 16:39:08 [unique_ch0] engine_0: ## 0:00:03 Skipping step 22.. SBY 16:39:08 [causal_ch0] engine_0: ## 0:00:03 Skipping step 21.. SBY 16:39:08 [csrw_mcycle_ch0] engine_0: ## 0:00:03 Skipping step 20.. SBY 16:39:08 [csrw_minstret_ch0] engine_0: ## 0:00:03 Skipping step 20.. SBY 16:39:08 [pc_fwd_ch0] engine_0: ## 0:00:03 Skipping step 22.. SBY 16:39:08 [reg_ch0] engine_0: ## 0:00:03 Skipping step 22.. SBY 16:39:08 [liveness_ch0] engine_0: ## 0:00:03 Skipping step 22.. SBY 16:39:08 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 11.. SBY 16:39:08 [unique_ch0] engine_0: ## 0:00:03 Skipping step 23.. SBY 16:39:08 [pc_bwd_ch0] engine_0: ## 0:00:03 Skipping step 22.. SBY 16:39:08 [causal_ch0] engine_0: ## 0:00:03 Skipping step 22.. SBY 16:39:08 [csrw_mcycle_ch0] engine_0: ## 0:00:03 Skipping step 21.. SBY 16:39:08 [csrw_minstret_ch0] engine_0: ## 0:00:03 Skipping step 21.. SBY 16:39:08 [pc_fwd_ch0] engine_0: ## 0:00:03 Skipping step 23.. SBY 16:39:08 [reg_ch0] engine_0: ## 0:00:03 Skipping step 23.. SBY 16:39:08 [liveness_ch0] engine_0: ## 0:00:03 Skipping step 23.. SBY 16:39:08 [unique_ch0] engine_0: ## 0:00:03 Skipping step 24.. SBY 16:39:08 [pc_bwd_ch0] engine_0: ## 0:00:03 Skipping step 23.. SBY 16:39:08 [causal_ch0] engine_0: ## 0:00:03 Skipping step 23.. SBY 16:39:08 [csrw_mcycle_ch0] engine_0: ## 0:00:03 Skipping step 22.. SBY 16:39:08 [csrw_minstret_ch0] engine_0: ## 0:00:03 Skipping step 22.. SBY 16:39:08 [pc_fwd_ch0] engine_0: ## 0:00:03 Skipping step 24.. SBY 16:39:08 [reg_ch0] engine_0: ## 0:00:03 Skipping step 24.. SBY 16:39:08 [liveness_ch0] engine_0: ## 0:00:03 Skipping step 24.. SBY 16:39:08 [unique_ch0] engine_0: ## 0:00:03 Skipping step 25.. SBY 16:39:08 [pc_bwd_ch0] engine_0: ## 0:00:03 Skipping step 24.. SBY 16:39:08 [csrw_mcycle_ch0] engine_0: ## 0:00:03 Skipping step 23.. SBY 16:39:08 [causal_ch0] engine_0: ## 0:00:03 Skipping step 24.. SBY 16:39:08 [csrw_minstret_ch0] engine_0: ## 0:00:03 Skipping step 23.. SBY 16:39:08 [pc_fwd_ch0] engine_0: ## 0:00:03 Skipping step 25.. SBY 16:39:08 [reg_ch0] engine_0: ## 0:00:03 Checking assertions in step 25.. SBY 16:39:08 [liveness_ch0] engine_0: ## 0:00:03 Skipping step 25.. SBY 16:39:08 [unique_ch0] engine_0: ## 0:00:04 Skipping step 26.. SBY 16:39:08 [pc_bwd_ch0] engine_0: ## 0:00:03 Skipping step 25.. SBY 16:39:08 [csrw_mcycle_ch0] engine_0: ## 0:00:03 Skipping step 24.. SBY 16:39:08 [causal_ch0] engine_0: ## 0:00:03 Skipping step 25.. SBY 16:39:08 [pc_fwd_ch0] engine_0: ## 0:00:04 Skipping step 26.. SBY 16:39:08 [csrw_minstret_ch0] engine_0: ## 0:00:03 Skipping step 24.. SBY 16:39:08 [liveness_ch0] engine_0: ## 0:00:04 Skipping step 26.. SBY 16:39:08 [unique_ch0] engine_0: ## 0:00:04 Skipping step 27.. SBY 16:39:08 [pc_bwd_ch0] engine_0: ## 0:00:04 Skipping step 26.. SBY 16:39:08 [pc_fwd_ch0] engine_0: ## 0:00:04 Skipping step 27.. SBY 16:39:08 [causal_ch0] engine_0: ## 0:00:04 Skipping step 26.. SBY 16:39:08 [csrw_mcycle_ch0] engine_0: ## 0:00:03 Skipping step 25.. SBY 16:39:08 [csrw_minstret_ch0] engine_0: ## 0:00:03 Skipping step 25.. SBY 16:39:08 [liveness_ch0] engine_0: ## 0:00:04 Skipping step 27.. SBY 16:39:08 [unique_ch0] engine_0: ## 0:00:04 Skipping step 28.. SBY 16:39:09 [pc_fwd_ch0] engine_0: ## 0:00:04 Skipping step 28.. SBY 16:39:09 [pc_bwd_ch0] engine_0: ## 0:00:04 Skipping step 27.. SBY 16:39:09 [causal_ch0] engine_0: ## 0:00:04 Skipping step 27.. SBY 16:39:09 [csrw_mcycle_ch0] engine_0: ## 0:00:04 Skipping step 26.. SBY 16:39:09 [liveness_ch0] engine_0: ## 0:00:04 Skipping step 28.. SBY 16:39:09 [csrw_minstret_ch0] engine_0: ## 0:00:04 Skipping step 26.. SBY 16:39:09 [unique_ch0] engine_0: ## 0:00:04 Skipping step 29.. SBY 16:39:09 [pc_fwd_ch0] engine_0: ## 0:00:04 Skipping step 29.. SBY 16:39:09 [pc_bwd_ch0] engine_0: ## 0:00:04 Skipping step 28.. SBY 16:39:09 [causal_ch0] engine_0: ## 0:00:04 Skipping step 28.. SBY 16:39:09 [liveness_ch0] engine_0: ## 0:00:04 Skipping step 29.. SBY 16:39:09 [csrw_mcycle_ch0] engine_0: ## 0:00:04 Skipping step 27.. SBY 16:39:09 [csrw_minstret_ch0] engine_0: ## 0:00:04 Skipping step 27.. SBY 16:39:09 [unique_ch0] engine_0: ## 0:00:04 Checking assertions in step 30.. SBY 16:39:09 [pc_fwd_ch0] engine_0: ## 0:00:04 Checking assertions in step 30.. SBY 16:39:09 [pc_bwd_ch0] engine_0: ## 0:00:04 Skipping step 29.. SBY 16:39:09 [liveness_ch0] engine_0: ## 0:00:04 Checking assertions in step 30.. SBY 16:39:09 [causal_ch0] engine_0: ## 0:00:04 Skipping step 29.. SBY 16:39:09 [csrw_mcycle_ch0] engine_0: ## 0:00:04 Skipping step 28.. SBY 16:39:09 [csrw_minstret_ch0] engine_0: ## 0:00:04 Skipping step 28.. SBY 16:39:09 [pc_bwd_ch0] engine_0: ## 0:00:04 Checking assertions in step 30.. SBY 16:39:09 [causal_ch0] engine_0: ## 0:00:04 Checking assertions in step 30.. SBY 16:39:09 [csrw_mcycle_ch0] engine_0: ## 0:00:04 Skipping step 29.. SBY 16:39:09 [csrw_minstret_ch0] engine_0: ## 0:00:04 Skipping step 29.. SBY 16:39:09 [csrw_mcycle_ch0] engine_0: ## 0:00:04 Checking assertions in step 30.. SBY 16:39:09 [csrw_minstret_ch0] engine_0: ## 0:00:04 Checking assertions in step 30.. SBY 16:39:11 [cover] engine_0: ## 0:00:06 Reached cover statement at rvfi_testbench.sv:39|cover_stmts.vh:1 in step 11. SBY 16:39:11 [cover] engine_0: ## 0:00:06 Writing trace to VCD file: engine_0/trace0.vcd SBY 16:39:11 [cover] engine_0: ## 0:00:07 Writing trace to Verilog testbench: engine_0/trace0_tb.v SBY 16:39:11 [cover] engine_0: ## 0:00:07 Writing trace to constraints file: engine_0/trace0.smtc SBY 16:39:11 [cover] engine_0: ## 0:00:07 Status: passed SBY 16:39:11 [cover] engine_0: finished (returncode=0) SBY 16:39:11 [cover] engine_0: Status returned by engine: pass SBY 16:39:11 [cover] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:11 (11) SBY 16:39:11 [cover] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:11 (11) SBY 16:39:11 [cover] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:39:11 [cover] DONE (PASS, rc=0) sby insn_bgeu_ch0.sby SBY 16:39:12 [insn_bgeu_ch0] Writing 'insn_bgeu_ch0/src/defines.sv'. SBY 16:39:12 [insn_bgeu_ch0] Writing 'insn_bgeu_ch0/src/insn_bgeu_ch0.sv'. SBY 16:39:12 [insn_bgeu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_bgeu_ch0/src/rvfi_macros.vh'. SBY 16:39:12 [insn_bgeu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_bgeu_ch0/src/rvfi_channel.sv'. SBY 16:39:12 [insn_bgeu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_bgeu_ch0/src/rvfi_testbench.sv'. SBY 16:39:12 [insn_bgeu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_bgeu_ch0/src/rvfi_insn_check.sv'. SBY 16:39:12 [insn_bgeu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_bgeu.v' to 'insn_bgeu_ch0/src/insn_bgeu.v'. SBY 16:39:12 [insn_bgeu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:12 [insn_bgeu_ch0] base: starting process "cd insn_bgeu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:16 [unique_ch0] engine_0: ## 0:00:11 Status: passed SBY 16:39:16 [unique_ch0] engine_0: finished (returncode=0) SBY 16:39:16 [unique_ch0] engine_0: Status returned by engine: pass SBY 16:39:16 [unique_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:16 (16) SBY 16:39:16 [unique_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:16 (16) SBY 16:39:16 [unique_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:39:16 [unique_ch0] DONE (PASS, rc=0) sby insn_blt_ch0.sby SBY 16:39:16 [insn_blt_ch0] Writing 'insn_blt_ch0/src/defines.sv'. SBY 16:39:16 [insn_blt_ch0] Writing 'insn_blt_ch0/src/insn_blt_ch0.sv'. SBY 16:39:16 [insn_blt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_blt_ch0/src/rvfi_macros.vh'. SBY 16:39:16 [insn_blt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_blt_ch0/src/rvfi_channel.sv'. SBY 16:39:16 [insn_blt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_blt_ch0/src/rvfi_testbench.sv'. SBY 16:39:16 [insn_blt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_blt_ch0/src/rvfi_insn_check.sv'. SBY 16:39:16 [insn_blt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_blt.v' to 'insn_blt_ch0/src/insn_blt.v'. SBY 16:39:16 [insn_blt_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:16 [csrw_minstret_ch0] engine_0: ## 0:00:11 Status: passed SBY 16:39:16 [insn_blt_ch0] base: starting process "cd insn_blt_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:16 [csrw_minstret_ch0] engine_0: finished (returncode=0) SBY 16:39:16 [csrw_minstret_ch0] engine_0: Status returned by engine: pass SBY 16:39:16 [csrw_minstret_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:16 (16) SBY 16:39:16 [csrw_minstret_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:16 (16) SBY 16:39:16 [csrw_minstret_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:39:16 [csrw_minstret_ch0] DONE (PASS, rc=0) sby insn_bltu_ch0.sby SBY 16:39:16 [csrw_mcycle_ch0] engine_0: ## 0:00:11 Status: passed SBY 16:39:16 [insn_bltu_ch0] Writing 'insn_bltu_ch0/src/defines.sv'. SBY 16:39:16 [insn_bltu_ch0] Writing 'insn_bltu_ch0/src/insn_bltu_ch0.sv'. SBY 16:39:16 [insn_bltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_bltu_ch0/src/rvfi_macros.vh'. SBY 16:39:16 [insn_bltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_bltu_ch0/src/rvfi_channel.sv'. SBY 16:39:16 [insn_bltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_bltu_ch0/src/rvfi_testbench.sv'. SBY 16:39:16 [insn_bltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_bltu_ch0/src/rvfi_insn_check.sv'. SBY 16:39:16 [insn_bltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_bltu.v' to 'insn_bltu_ch0/src/insn_bltu.v'. SBY 16:39:16 [insn_bltu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:16 [insn_bltu_ch0] base: starting process "cd insn_bltu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:16 [csrw_mcycle_ch0] engine_0: finished (returncode=0) SBY 16:39:16 [csrw_mcycle_ch0] engine_0: Status returned by engine: pass SBY 16:39:16 [csrw_mcycle_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:16 (16) SBY 16:39:16 [csrw_mcycle_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:16 (16) SBY 16:39:16 [csrw_mcycle_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:39:16 [csrw_mcycle_ch0] DONE (PASS, rc=0) sby insn_bne_ch0.sby SBY 16:39:16 [insn_bne_ch0] Writing 'insn_bne_ch0/src/defines.sv'. SBY 16:39:16 [insn_bne_ch0] Writing 'insn_bne_ch0/src/insn_bne_ch0.sv'. SBY 16:39:16 [insn_bne_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_bne_ch0/src/rvfi_macros.vh'. SBY 16:39:16 [insn_bne_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_bne_ch0/src/rvfi_channel.sv'. SBY 16:39:16 [insn_bne_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_bne_ch0/src/rvfi_testbench.sv'. SBY 16:39:16 [insn_bne_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_bne_ch0/src/rvfi_insn_check.sv'. SBY 16:39:16 [insn_bne_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_bne.v' to 'insn_bne_ch0/src/insn_bne.v'. SBY 16:39:16 [insn_bne_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:16 [insn_bne_ch0] base: starting process "cd insn_bne_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:17 [causal_ch0] engine_0: ## 0:00:12 Status: passed SBY 16:39:17 [pc_bwd_ch0] engine_0: ## 0:00:12 Status: passed SBY 16:39:17 [causal_ch0] engine_0: finished (returncode=0) SBY 16:39:17 [causal_ch0] engine_0: Status returned by engine: pass SBY 16:39:17 [causal_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:17 (17) SBY 16:39:17 [causal_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:17 (17) SBY 16:39:17 [causal_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:39:17 [causal_ch0] DONE (PASS, rc=0) sby insn_c_add_ch0.sby SBY 16:39:17 [pc_bwd_ch0] engine_0: finished (returncode=0) SBY 16:39:17 [pc_bwd_ch0] engine_0: Status returned by engine: pass SBY 16:39:17 [pc_bwd_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:17 (17) SBY 16:39:17 [pc_bwd_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:17 (17) SBY 16:39:17 [pc_bwd_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:39:17 [pc_bwd_ch0] DONE (PASS, rc=0) sby insn_c_addi16sp_ch0.sby SBY 16:39:17 [insn_c_add_ch0] Writing 'insn_c_add_ch0/src/defines.sv'. SBY 16:39:17 [insn_c_add_ch0] Writing 'insn_c_add_ch0/src/insn_c_add_ch0.sv'. SBY 16:39:17 [insn_c_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_add_ch0/src/rvfi_macros.vh'. SBY 16:39:17 [insn_c_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_add_ch0/src/rvfi_channel.sv'. SBY 16:39:17 [insn_c_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_add_ch0/src/rvfi_testbench.sv'. SBY 16:39:17 [insn_c_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_add_ch0/src/rvfi_insn_check.sv'. SBY 16:39:17 [insn_c_add_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_add.v' to 'insn_c_add_ch0/src/insn_c_add.v'. SBY 16:39:17 [insn_c_add_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:17 [insn_c_add_ch0] base: starting process "cd insn_c_add_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:17 [insn_c_addi16sp_ch0] Writing 'insn_c_addi16sp_ch0/src/defines.sv'. SBY 16:39:17 [insn_c_addi16sp_ch0] Writing 'insn_c_addi16sp_ch0/src/insn_c_addi16sp_ch0.sv'. SBY 16:39:17 [insn_c_addi16sp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_addi16sp_ch0/src/rvfi_macros.vh'. SBY 16:39:17 [insn_c_addi16sp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_addi16sp_ch0/src/rvfi_channel.sv'. SBY 16:39:17 [insn_c_addi16sp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_addi16sp_ch0/src/rvfi_testbench.sv'. SBY 16:39:17 [insn_c_addi16sp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_addi16sp_ch0/src/rvfi_insn_check.sv'. SBY 16:39:17 [insn_c_addi16sp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_addi16sp.v' to 'insn_c_addi16sp_ch0/src/insn_c_addi16sp.v'. SBY 16:39:17 [insn_c_addi16sp_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:17 [insn_c_addi16sp_ch0] base: starting process "cd insn_c_addi16sp_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:17 [insn_bgeu_ch0] base: finished (returncode=0) SBY 16:39:17 [insn_bgeu_ch0] smt2: starting process "cd insn_bgeu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:17 [insn_bgeu_ch0] smt2: finished (returncode=0) SBY 16:39:17 [insn_bgeu_ch0] engine_0: starting process "cd insn_bgeu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:17 [insn_bgeu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:18 [insn_bgeu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:18 [insn_bgeu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:18 [insn_bgeu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:18 [insn_bgeu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:18 [insn_bgeu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:18 [insn_bgeu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:18 [insn_bgeu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:19 [insn_bgeu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:19 [insn_bgeu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:19 [insn_bgeu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:19 [insn_bgeu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:19 [insn_bgeu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:19 [insn_bgeu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:19 [insn_bgeu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:20 [insn_bgeu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:20 [insn_bgeu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:20 [insn_bgeu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:20 [insn_bgeu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:20 [insn_bgeu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:20 [insn_bgeu_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:21 [insn_bgeu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:22 [insn_bltu_ch0] base: finished (returncode=0) SBY 16:39:22 [insn_bltu_ch0] smt2: starting process "cd insn_bltu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:22 [insn_blt_ch0] base: finished (returncode=0) SBY 16:39:22 [insn_blt_ch0] smt2: starting process "cd insn_blt_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:22 [insn_blt_ch0] smt2: finished (returncode=0) SBY 16:39:22 [insn_blt_ch0] engine_0: starting process "cd insn_blt_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:22 [insn_bltu_ch0] smt2: finished (returncode=0) SBY 16:39:22 [insn_bltu_ch0] engine_0: starting process "cd insn_bltu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:22 [insn_bltu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:22 [insn_blt_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:22 [insn_bne_ch0] base: finished (returncode=0) SBY 16:39:22 [insn_bne_ch0] smt2: starting process "cd insn_bne_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:22 [insn_bltu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:22 [insn_blt_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:22 [insn_bne_ch0] smt2: finished (returncode=0) SBY 16:39:22 [insn_bne_ch0] engine_0: starting process "cd insn_bne_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:22 [insn_bne_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:22 [insn_c_addi16sp_ch0] base: finished (returncode=0) SBY 16:39:22 [insn_c_addi16sp_ch0] smt2: starting process "cd insn_c_addi16sp_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:22 [insn_c_add_ch0] base: finished (returncode=0) SBY 16:39:22 [insn_c_add_ch0] smt2: starting process "cd insn_c_add_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:22 [insn_bltu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:22 [insn_blt_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:22 [insn_bne_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:22 [insn_bltu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:22 [insn_blt_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:23 [insn_bne_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:23 [insn_c_addi16sp_ch0] smt2: finished (returncode=0) SBY 16:39:23 [insn_c_addi16sp_ch0] engine_0: starting process "cd insn_c_addi16sp_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:23 [insn_bltu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:23 [insn_blt_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:23 [insn_c_add_ch0] smt2: finished (returncode=0) SBY 16:39:23 [insn_c_add_ch0] engine_0: starting process "cd insn_c_add_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:23 [insn_c_addi16sp_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:23 [insn_bne_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:23 [insn_c_add_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:23 [insn_bltu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:23 [insn_blt_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:23 [insn_bne_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:23 [insn_bltu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:23 [insn_c_addi16sp_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:23 [insn_blt_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:23 [insn_c_add_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:23 [insn_bne_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:23 [insn_bltu_ch0] engine_0: ## 0:00:00 Skipping step 6.. SBY 16:39:23 [insn_c_addi16sp_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:23 [insn_blt_ch0] engine_0: ## 0:00:00 Skipping step 6.. SBY 16:39:23 [insn_c_add_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:23 [insn_bne_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:23 [insn_bltu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:23 [insn_blt_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:23 [insn_c_addi16sp_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:23 [insn_c_add_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:23 [insn_bne_ch0] engine_0: ## 0:00:00 Skipping step 6.. SBY 16:39:23 [insn_bltu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:23 [insn_blt_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:23 [insn_c_addi16sp_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:23 [insn_c_add_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:23 [insn_bne_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:23 [insn_bltu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:23 [insn_blt_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:23 [insn_c_addi16sp_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:23 [insn_c_add_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:23 [insn_bne_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:23 [insn_bltu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:24 [insn_blt_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:24 [insn_c_addi16sp_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:24 [insn_c_add_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:24 [insn_bne_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:24 [insn_bltu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:24 [insn_blt_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:24 [insn_c_addi16sp_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:24 [insn_c_add_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:24 [insn_bne_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:24 [insn_bltu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:24 [insn_blt_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:24 [insn_c_addi16sp_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:24 [insn_c_add_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:24 [insn_bne_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:24 [insn_bltu_ch0] engine_0: ## 0:00:01 Skipping step 13.. SBY 16:39:24 [insn_blt_ch0] engine_0: ## 0:00:01 Skipping step 13.. SBY 16:39:24 [insn_c_addi16sp_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:24 [insn_c_add_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:24 [insn_bne_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:24 [insn_bltu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:24 [insn_blt_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:24 [insn_c_addi16sp_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:24 [insn_c_add_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:24 [insn_bltu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:24 [insn_bne_ch0] engine_0: ## 0:00:01 Skipping step 13.. SBY 16:39:24 [insn_blt_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:24 [insn_c_addi16sp_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:24 [insn_c_add_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:24 [insn_bltu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:24 [insn_bne_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:24 [insn_blt_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:24 [insn_c_addi16sp_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:24 [insn_c_add_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:24 [insn_bltu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:24 [insn_bne_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:25 [insn_blt_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:25 [insn_bltu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:25 [insn_c_addi16sp_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:25 [insn_c_add_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:25 [insn_bne_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:25 [insn_blt_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:25 [insn_bltu_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:25 [insn_c_addi16sp_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:25 [insn_c_add_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:25 [insn_bne_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:25 [insn_blt_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:25 [insn_bltu_ch0] engine_0: ## 0:00:02 Checking assertions in step 20.. SBY 16:39:25 [insn_c_add_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:25 [insn_c_addi16sp_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:25 [insn_bne_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:25 [insn_blt_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:25 [insn_c_add_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:25 [insn_c_addi16sp_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:25 [insn_bne_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:25 [insn_c_add_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:25 [insn_c_addi16sp_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:25 [insn_bne_ch0] engine_0: ## 0:00:02 Checking assertions in step 20.. SBY 16:39:25 [insn_c_add_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:25 [insn_c_addi16sp_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:25 [insn_c_add_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:25 [insn_c_addi16sp_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:26 [insn_c_add_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:26 [insn_c_addi16sp_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:26 [insn_c_add_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:26 [insn_c_addi16sp_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:38 [liveness_ch0] engine_0: ## 0:00:33 Status: passed SBY 16:39:38 [liveness_ch0] engine_0: finished (returncode=0) SBY 16:39:38 [liveness_ch0] engine_0: Status returned by engine: pass SBY 16:39:38 [liveness_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:38 (38) SBY 16:39:38 [liveness_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:38 (38) SBY 16:39:38 [liveness_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:39:38 [liveness_ch0] DONE (PASS, rc=0) sby insn_c_addi4spn_ch0.sby SBY 16:39:38 [insn_c_addi4spn_ch0] Writing 'insn_c_addi4spn_ch0/src/defines.sv'. SBY 16:39:38 [insn_c_addi4spn_ch0] Writing 'insn_c_addi4spn_ch0/src/insn_c_addi4spn_ch0.sv'. SBY 16:39:38 [insn_c_addi4spn_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_addi4spn_ch0/src/rvfi_macros.vh'. SBY 16:39:38 [insn_c_addi4spn_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_addi4spn_ch0/src/rvfi_channel.sv'. SBY 16:39:38 [insn_c_addi4spn_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_addi4spn_ch0/src/rvfi_testbench.sv'. SBY 16:39:38 [insn_c_addi4spn_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_addi4spn_ch0/src/rvfi_insn_check.sv'. SBY 16:39:38 [insn_c_addi4spn_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_addi4spn.v' to 'insn_c_addi4spn_ch0/src/insn_c_addi4spn.v'. SBY 16:39:38 [insn_c_addi4spn_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:38 [insn_c_addi4spn_ch0] base: starting process "cd insn_c_addi4spn_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:42 [pc_fwd_ch0] engine_0: ## 0:00:37 Status: passed SBY 16:39:42 [pc_fwd_ch0] engine_0: finished (returncode=0) SBY 16:39:42 [pc_fwd_ch0] engine_0: Status returned by engine: pass SBY 16:39:42 [pc_fwd_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:42 (42) SBY 16:39:42 [pc_fwd_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:42 (42) SBY 16:39:42 [pc_fwd_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:39:42 [pc_fwd_ch0] DONE (PASS, rc=0) sby insn_c_addi_ch0.sby SBY 16:39:42 [insn_c_addi_ch0] Writing 'insn_c_addi_ch0/src/defines.sv'. SBY 16:39:42 [insn_c_addi_ch0] Writing 'insn_c_addi_ch0/src/insn_c_addi_ch0.sv'. SBY 16:39:42 [insn_c_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_addi_ch0/src/rvfi_macros.vh'. SBY 16:39:42 [insn_c_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_addi_ch0/src/rvfi_channel.sv'. SBY 16:39:42 [insn_c_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_addi_ch0/src/rvfi_testbench.sv'. SBY 16:39:42 [insn_c_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_addi_ch0/src/rvfi_insn_check.sv'. SBY 16:39:42 [insn_c_addi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_addi.v' to 'insn_c_addi_ch0/src/insn_c_addi.v'. SBY 16:39:42 [insn_c_addi_ch0] engine_0: smtbmc --nopresat boolector SBY 16:39:42 [insn_c_addi_ch0] base: starting process "cd insn_c_addi_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:39:44 [insn_c_addi4spn_ch0] base: finished (returncode=0) SBY 16:39:44 [insn_c_addi4spn_ch0] smt2: starting process "cd insn_c_addi4spn_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:44 [insn_c_addi4spn_ch0] smt2: finished (returncode=0) SBY 16:39:44 [insn_c_addi4spn_ch0] engine_0: starting process "cd insn_c_addi4spn_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:44 [insn_c_addi4spn_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:44 [insn_c_addi4spn_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:45 [insn_c_addi4spn_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:45 [insn_c_addi4spn_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:45 [insn_c_addi4spn_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:45 [insn_c_addi4spn_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:45 [insn_c_addi4spn_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:45 [insn_c_addi4spn_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:46 [insn_c_addi4spn_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:46 [insn_c_addi4spn_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:46 [insn_c_addi4spn_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:46 [insn_c_addi4spn_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:46 [insn_c_addi4spn_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:46 [insn_c_addi4spn_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:46 [insn_c_addi4spn_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:47 [insn_c_addi4spn_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:47 [insn_c_addi4spn_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:47 [insn_c_addi4spn_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:47 [insn_c_addi4spn_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:47 [insn_c_addi4spn_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:47 [insn_c_addi4spn_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:39:47 [insn_c_addi4spn_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:39:48 [insn_c_addi_ch0] base: finished (returncode=0) SBY 16:39:48 [insn_c_addi_ch0] smt2: starting process "cd insn_c_addi_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:39:48 [insn_c_addi_ch0] smt2: finished (returncode=0) SBY 16:39:48 [insn_c_addi_ch0] engine_0: starting process "cd insn_c_addi_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:39:48 [insn_c_addi_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:39:49 [insn_c_addi_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:39:49 [insn_c_addi_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:39:49 [insn_c_addi_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:39:49 [insn_c_addi_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:39:49 [insn_c_addi_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:39:49 [insn_c_addi_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:39:49 [insn_c_addi_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:39:50 [insn_c_addi_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:39:50 [insn_c_addi_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:39:50 [insn_c_addi_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:39:50 [insn_c_addi_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:39:50 [insn_c_addi_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:39:50 [insn_c_addi_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:39:50 [insn_c_addi_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:39:51 [insn_c_addi_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:39:51 [insn_c_addi_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:39:51 [insn_c_addi_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:39:51 [insn_c_addi_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:39:51 [insn_c_addi_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:39:51 [insn_c_addi_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:39:51 [insn_c_addi_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:40:08 [insn_auipc_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:08 [insn_andi_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:08 [insn_add_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:08 [insn_and_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:08 [insn_beq_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:08 [insn_bge_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:08 [insn_addi_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:08 [reg_ch0] engine_0: ## 0:01:04 waiting for solver (1 minute) SBY 16:40:21 [insn_bgeu_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:25 [insn_bltu_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:25 [insn_blt_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:25 [insn_bne_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:26 [insn_c_add_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:26 [insn_c_addi16sp_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:34 [insn_andi_ch0] engine_0: ## 0:01:29 Status: passed SBY 16:40:34 [insn_andi_ch0] engine_0: finished (returncode=0) SBY 16:40:34 [insn_andi_ch0] engine_0: Status returned by engine: pass SBY 16:40:34 [insn_andi_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:34 (94) SBY 16:40:34 [insn_andi_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:34 (94) SBY 16:40:34 [insn_andi_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:40:34 [insn_andi_ch0] DONE (PASS, rc=0) sby insn_c_and_ch0.sby SBY 16:40:34 [insn_c_and_ch0] Writing 'insn_c_and_ch0/src/defines.sv'. SBY 16:40:34 [insn_c_and_ch0] Writing 'insn_c_and_ch0/src/insn_c_and_ch0.sv'. SBY 16:40:34 [insn_c_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_and_ch0/src/rvfi_macros.vh'. SBY 16:40:34 [insn_c_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_and_ch0/src/rvfi_channel.sv'. SBY 16:40:34 [insn_c_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_and_ch0/src/rvfi_testbench.sv'. SBY 16:40:34 [insn_c_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_and_ch0/src/rvfi_insn_check.sv'. SBY 16:40:34 [insn_c_and_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_and.v' to 'insn_c_and_ch0/src/insn_c_and.v'. SBY 16:40:34 [insn_c_and_ch0] engine_0: smtbmc --nopresat boolector SBY 16:40:34 [insn_c_and_ch0] base: starting process "cd insn_c_and_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:40:35 [insn_and_ch0] engine_0: ## 0:01:31 Status: passed SBY 16:40:36 [insn_and_ch0] engine_0: finished (returncode=0) SBY 16:40:36 [insn_and_ch0] engine_0: Status returned by engine: pass SBY 16:40:36 [insn_and_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:35 (95) SBY 16:40:36 [insn_and_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:35 (95) SBY 16:40:36 [insn_and_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:40:36 [insn_and_ch0] DONE (PASS, rc=0) sby insn_c_andi_ch0.sby SBY 16:40:36 [insn_c_andi_ch0] Writing 'insn_c_andi_ch0/src/defines.sv'. SBY 16:40:36 [insn_c_andi_ch0] Writing 'insn_c_andi_ch0/src/insn_c_andi_ch0.sv'. SBY 16:40:36 [insn_c_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_andi_ch0/src/rvfi_macros.vh'. SBY 16:40:36 [insn_c_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_andi_ch0/src/rvfi_channel.sv'. SBY 16:40:36 [insn_c_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_andi_ch0/src/rvfi_testbench.sv'. SBY 16:40:36 [insn_c_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_andi_ch0/src/rvfi_insn_check.sv'. SBY 16:40:36 [insn_c_andi_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_andi.v' to 'insn_c_andi_ch0/src/insn_c_andi.v'. SBY 16:40:36 [insn_c_andi_ch0] engine_0: smtbmc --nopresat boolector SBY 16:40:36 [insn_c_andi_ch0] base: starting process "cd insn_c_andi_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:40:40 [insn_c_and_ch0] base: finished (returncode=0) SBY 16:40:40 [insn_c_and_ch0] smt2: starting process "cd insn_c_and_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:40:40 [insn_c_and_ch0] smt2: finished (returncode=0) SBY 16:40:40 [insn_c_and_ch0] engine_0: starting process "cd insn_c_and_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:40:40 [insn_c_and_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:40:40 [insn_c_and_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:40:40 [insn_c_and_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:40:40 [insn_c_and_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:40:40 [insn_c_and_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:40:41 [insn_c_and_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:40:41 [insn_c_and_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:40:41 [insn_c_and_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:40:41 [insn_c_and_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:40:41 [insn_c_and_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:40:41 [insn_c_andi_ch0] base: finished (returncode=0) SBY 16:40:41 [insn_c_andi_ch0] smt2: starting process "cd insn_c_andi_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:40:41 [insn_c_and_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:40:41 [insn_c_andi_ch0] smt2: finished (returncode=0) SBY 16:40:41 [insn_c_andi_ch0] engine_0: starting process "cd insn_c_andi_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:40:41 [insn_c_andi_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:40:41 [insn_c_and_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:40:42 [insn_c_andi_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:40:42 [insn_c_and_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:40:42 [insn_c_andi_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:40:42 [insn_c_and_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:40:42 [insn_c_andi_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:40:42 [insn_c_and_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:40:42 [insn_c_andi_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:40:42 [insn_c_and_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:40:42 [insn_c_andi_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:40:42 [insn_c_and_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:40:42 [insn_c_andi_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:40:42 [insn_c_and_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:40:42 [insn_c_andi_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:40:43 [insn_c_and_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:40:43 [insn_c_andi_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:40:43 [insn_c_and_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:40:43 [insn_c_andi_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:40:43 [insn_c_and_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:40:43 [insn_c_andi_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:40:43 [insn_c_and_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:40:43 [insn_c_andi_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:40:43 [insn_c_andi_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:40:43 [insn_c_andi_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:40:43 [insn_c_andi_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:40:44 [insn_c_andi_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:40:44 [insn_c_andi_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:40:44 [insn_c_andi_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:40:44 [insn_c_andi_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:40:44 [insn_c_andi_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:40:44 [insn_c_andi_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:40:44 [insn_c_andi_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:40:48 [insn_c_addi4spn_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:48 [insn_add_ch0] engine_0: ## 0:01:43 Status: passed SBY 16:40:48 [insn_add_ch0] engine_0: finished (returncode=0) SBY 16:40:48 [insn_add_ch0] engine_0: Status returned by engine: pass SBY 16:40:48 [insn_add_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:48 (108) SBY 16:40:48 [insn_add_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:48 (108) SBY 16:40:48 [insn_add_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:40:48 [insn_add_ch0] DONE (PASS, rc=0) sby insn_c_beqz_ch0.sby SBY 16:40:48 [insn_c_beqz_ch0] Writing 'insn_c_beqz_ch0/src/defines.sv'. SBY 16:40:48 [insn_c_beqz_ch0] Writing 'insn_c_beqz_ch0/src/insn_c_beqz_ch0.sv'. SBY 16:40:48 [insn_c_beqz_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_beqz_ch0/src/rvfi_macros.vh'. SBY 16:40:48 [insn_c_beqz_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_beqz_ch0/src/rvfi_channel.sv'. SBY 16:40:48 [insn_c_beqz_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_beqz_ch0/src/rvfi_testbench.sv'. SBY 16:40:48 [insn_c_beqz_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_beqz_ch0/src/rvfi_insn_check.sv'. SBY 16:40:48 [insn_c_beqz_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_beqz.v' to 'insn_c_beqz_ch0/src/insn_c_beqz.v'. SBY 16:40:48 [insn_c_beqz_ch0] engine_0: smtbmc --nopresat boolector SBY 16:40:48 [insn_c_beqz_ch0] base: starting process "cd insn_c_beqz_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:40:52 [insn_c_addi_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:40:54 [insn_c_beqz_ch0] base: finished (returncode=0) SBY 16:40:54 [insn_c_beqz_ch0] smt2: starting process "cd insn_c_beqz_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:40:54 [insn_c_beqz_ch0] smt2: finished (returncode=0) SBY 16:40:54 [insn_c_beqz_ch0] engine_0: starting process "cd insn_c_beqz_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:40:54 [insn_c_beqz_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:40:54 [insn_c_beqz_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:40:55 [insn_c_beqz_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:40:55 [insn_c_beqz_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:40:55 [insn_c_beqz_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:40:55 [insn_c_beqz_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:40:55 [insn_c_beqz_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:40:55 [insn_c_beqz_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:40:55 [insn_c_beqz_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:40:56 [insn_c_beqz_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:40:56 [insn_c_beqz_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:40:56 [insn_c_beqz_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:40:56 [insn_c_beqz_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:40:56 [insn_c_beqz_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:40:56 [insn_c_beqz_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:40:56 [insn_c_beqz_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:40:57 [insn_c_beqz_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:40:57 [insn_c_beqz_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:40:57 [insn_c_beqz_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:40:57 [insn_c_beqz_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:40:57 [insn_c_beqz_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:40:57 [insn_c_beqz_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:41:14 [insn_addi_ch0] engine_0: ## 0:02:09 Status: passed SBY 16:41:14 [insn_addi_ch0] engine_0: finished (returncode=0) SBY 16:41:14 [insn_addi_ch0] engine_0: Status returned by engine: pass SBY 16:41:14 [insn_addi_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:14 (134) SBY 16:41:14 [insn_addi_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:14 (134) SBY 16:41:14 [insn_addi_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:41:14 [insn_addi_ch0] DONE (PASS, rc=0) sby insn_c_bnez_ch0.sby SBY 16:41:14 [insn_c_bnez_ch0] Writing 'insn_c_bnez_ch0/src/defines.sv'. SBY 16:41:14 [insn_c_bnez_ch0] Writing 'insn_c_bnez_ch0/src/insn_c_bnez_ch0.sv'. SBY 16:41:14 [insn_c_bnez_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_bnez_ch0/src/rvfi_macros.vh'. SBY 16:41:14 [insn_c_bnez_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_bnez_ch0/src/rvfi_channel.sv'. SBY 16:41:14 [insn_c_bnez_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_bnez_ch0/src/rvfi_testbench.sv'. SBY 16:41:14 [insn_c_bnez_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_bnez_ch0/src/rvfi_insn_check.sv'. SBY 16:41:14 [insn_c_bnez_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_bnez.v' to 'insn_c_bnez_ch0/src/insn_c_bnez.v'. SBY 16:41:14 [insn_c_bnez_ch0] engine_0: smtbmc --nopresat boolector SBY 16:41:14 [insn_c_bnez_ch0] base: starting process "cd insn_c_bnez_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:41:20 [insn_c_bnez_ch0] base: finished (returncode=0) SBY 16:41:20 [insn_c_bnez_ch0] smt2: starting process "cd insn_c_bnez_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:41:20 [insn_c_bnez_ch0] smt2: finished (returncode=0) SBY 16:41:20 [insn_c_bnez_ch0] engine_0: starting process "cd insn_c_bnez_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:41:20 [insn_c_bnez_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:41:20 [insn_c_bnez_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:41:21 [insn_c_bnez_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:41:21 [insn_c_bnez_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:41:21 [insn_c_bnez_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:41:21 [insn_c_bnez_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:41:21 [insn_c_bnez_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:41:21 [insn_c_bnez_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:41:21 [insn_c_bnez_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:41:22 [insn_c_bnez_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:41:22 [insn_c_bnez_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:41:22 [insn_c_bnez_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:41:22 [insn_c_bnez_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:41:22 [insn_c_bnez_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:41:22 [insn_c_bnez_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:41:23 [insn_c_bnez_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:41:23 [insn_c_bnez_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:41:23 [insn_c_bnez_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:41:23 [insn_c_bnez_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:41:23 [insn_c_bnez_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:41:23 [insn_c_bnez_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:41:23 [insn_c_bnez_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:41:29 [insn_c_add_ch0] engine_0: ## 0:02:05 Status: passed SBY 16:41:29 [insn_c_add_ch0] engine_0: finished (returncode=0) SBY 16:41:29 [insn_c_add_ch0] engine_0: Status returned by engine: pass SBY 16:41:29 [insn_c_add_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:11 (131) SBY 16:41:29 [insn_c_add_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:11 (131) SBY 16:41:29 [insn_c_add_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:41:29 [insn_c_add_ch0] DONE (PASS, rc=0) sby insn_c_j_ch0.sby SBY 16:41:29 [insn_c_j_ch0] Writing 'insn_c_j_ch0/src/defines.sv'. SBY 16:41:29 [insn_c_j_ch0] Writing 'insn_c_j_ch0/src/insn_c_j_ch0.sv'. SBY 16:41:29 [insn_c_j_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_j_ch0/src/rvfi_macros.vh'. SBY 16:41:29 [insn_c_j_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_j_ch0/src/rvfi_channel.sv'. SBY 16:41:29 [insn_c_j_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_j_ch0/src/rvfi_testbench.sv'. SBY 16:41:29 [insn_c_j_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_j_ch0/src/rvfi_insn_check.sv'. SBY 16:41:29 [insn_c_j_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_j.v' to 'insn_c_j_ch0/src/insn_c_j.v'. SBY 16:41:29 [insn_c_j_ch0] engine_0: smtbmc --nopresat boolector SBY 16:41:29 [insn_c_j_ch0] base: starting process "cd insn_c_j_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:41:34 [insn_c_j_ch0] base: finished (returncode=0) SBY 16:41:34 [insn_c_j_ch0] smt2: starting process "cd insn_c_j_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:41:34 [insn_c_j_ch0] smt2: finished (returncode=0) SBY 16:41:34 [insn_c_j_ch0] engine_0: starting process "cd insn_c_j_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:41:34 [insn_c_j_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:41:34 [insn_c_j_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:41:35 [insn_c_j_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:41:35 [insn_c_j_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:41:35 [insn_c_j_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:41:35 [insn_c_j_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:41:35 [insn_c_j_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:41:35 [insn_c_j_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:41:35 [insn_c_j_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:41:36 [insn_c_j_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:41:36 [insn_c_j_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:41:36 [insn_c_j_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:41:36 [insn_c_j_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:41:36 [insn_c_j_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:41:36 [insn_c_j_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:41:36 [insn_c_j_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:41:37 [insn_c_j_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:41:37 [insn_c_addi_ch0] engine_0: ## 0:01:48 Status: passed SBY 16:41:37 [insn_c_addi_ch0] engine_0: finished (returncode=0) SBY 16:41:37 [insn_c_addi_ch0] engine_0: Status returned by engine: pass SBY 16:41:37 [insn_c_addi_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:54 (114) SBY 16:41:37 [insn_c_addi_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:54 (114) SBY 16:41:37 [insn_c_addi_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:41:37 [insn_c_addi_ch0] DONE (PASS, rc=0) sby insn_c_jal_ch0.sby SBY 16:41:37 [insn_c_j_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:41:37 [insn_c_jal_ch0] Writing 'insn_c_jal_ch0/src/defines.sv'. SBY 16:41:37 [insn_c_jal_ch0] Writing 'insn_c_jal_ch0/src/insn_c_jal_ch0.sv'. SBY 16:41:37 [insn_c_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_jal_ch0/src/rvfi_macros.vh'. SBY 16:41:37 [insn_c_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_jal_ch0/src/rvfi_channel.sv'. SBY 16:41:37 [insn_c_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_jal_ch0/src/rvfi_testbench.sv'. SBY 16:41:37 [insn_c_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_jal_ch0/src/rvfi_insn_check.sv'. SBY 16:41:37 [insn_c_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_jal.v' to 'insn_c_jal_ch0/src/insn_c_jal.v'. SBY 16:41:37 [insn_c_jal_ch0] engine_0: smtbmc --nopresat boolector SBY 16:41:37 [insn_c_jal_ch0] base: starting process "cd insn_c_jal_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:41:37 [insn_c_j_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:41:37 [insn_c_j_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:41:37 [insn_c_j_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:41:37 [insn_c_j_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:41:39 [insn_beq_ch0] engine_0: ## 0:02:34 Status: passed SBY 16:41:39 [insn_beq_ch0] engine_0: finished (returncode=0) SBY 16:41:39 [insn_beq_ch0] engine_0: Status returned by engine: pass SBY 16:41:39 [insn_beq_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:39 (159) SBY 16:41:39 [insn_beq_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:38 (158) SBY 16:41:39 [insn_beq_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:41:39 [insn_beq_ch0] DONE (PASS, rc=0) sby insn_c_jalr_ch0.sby SBY 16:41:39 [insn_c_jalr_ch0] Writing 'insn_c_jalr_ch0/src/defines.sv'. SBY 16:41:39 [insn_c_jalr_ch0] Writing 'insn_c_jalr_ch0/src/insn_c_jalr_ch0.sv'. SBY 16:41:39 [insn_c_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_jalr_ch0/src/rvfi_macros.vh'. SBY 16:41:39 [insn_c_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_jalr_ch0/src/rvfi_channel.sv'. SBY 16:41:39 [insn_c_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_jalr_ch0/src/rvfi_testbench.sv'. SBY 16:41:39 [insn_c_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_jalr_ch0/src/rvfi_insn_check.sv'. SBY 16:41:39 [insn_c_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_jalr.v' to 'insn_c_jalr_ch0/src/insn_c_jalr.v'. SBY 16:41:39 [insn_c_jalr_ch0] engine_0: smtbmc --nopresat boolector SBY 16:41:39 [insn_c_jalr_ch0] base: starting process "cd insn_c_jalr_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:41:40 [insn_c_addi16sp_ch0] engine_0: ## 0:02:17 Status: passed SBY 16:41:40 [insn_c_addi16sp_ch0] engine_0: finished (returncode=0) SBY 16:41:40 [insn_c_addi16sp_ch0] engine_0: Status returned by engine: pass SBY 16:41:40 [insn_c_addi16sp_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:23 (143) SBY 16:41:40 [insn_c_addi16sp_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:41:40 [insn_c_addi16sp_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:41:40 [insn_c_addi16sp_ch0] DONE (PASS, rc=0) sby insn_c_jr_ch0.sby SBY 16:41:40 [insn_c_jr_ch0] Writing 'insn_c_jr_ch0/src/defines.sv'. SBY 16:41:40 [insn_c_jr_ch0] Writing 'insn_c_jr_ch0/src/insn_c_jr_ch0.sv'. SBY 16:41:40 [insn_c_jr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_jr_ch0/src/rvfi_macros.vh'. SBY 16:41:40 [insn_c_jr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_jr_ch0/src/rvfi_channel.sv'. SBY 16:41:40 [insn_c_jr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_jr_ch0/src/rvfi_testbench.sv'. SBY 16:41:40 [insn_c_jr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_jr_ch0/src/rvfi_insn_check.sv'. SBY 16:41:40 [insn_c_jr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_jr.v' to 'insn_c_jr_ch0/src/insn_c_jr.v'. SBY 16:41:40 [insn_c_jr_ch0] engine_0: smtbmc --nopresat boolector SBY 16:41:40 [insn_c_jr_ch0] base: starting process "cd insn_c_jr_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:41:42 [insn_c_jal_ch0] base: finished (returncode=0) SBY 16:41:42 [insn_c_jal_ch0] smt2: starting process "cd insn_c_jal_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:41:42 [insn_c_jal_ch0] smt2: finished (returncode=0) SBY 16:41:42 [insn_c_jal_ch0] engine_0: starting process "cd insn_c_jal_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:41:42 [insn_c_jal_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:41:42 [insn_c_jal_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:41:42 [insn_c_jal_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:41:42 [insn_auipc_ch0] engine_0: ## 0:02:38 Status: passed SBY 16:41:42 [insn_auipc_ch0] engine_0: finished (returncode=0) SBY 16:41:42 [insn_auipc_ch0] engine_0: Status returned by engine: pass SBY 16:41:42 [insn_auipc_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:42 (162) SBY 16:41:42 [insn_auipc_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:42 (162) SBY 16:41:42 [insn_auipc_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:41:42 [insn_auipc_ch0] DONE (PASS, rc=0) sby insn_c_li_ch0.sby SBY 16:41:42 [insn_c_jal_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:41:43 [insn_c_li_ch0] Writing 'insn_c_li_ch0/src/defines.sv'. SBY 16:41:43 [insn_c_li_ch0] Writing 'insn_c_li_ch0/src/insn_c_li_ch0.sv'. SBY 16:41:43 [insn_c_li_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_li_ch0/src/rvfi_macros.vh'. SBY 16:41:43 [insn_c_li_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_li_ch0/src/rvfi_channel.sv'. SBY 16:41:43 [insn_c_li_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_li_ch0/src/rvfi_testbench.sv'. SBY 16:41:43 [insn_c_li_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_li_ch0/src/rvfi_insn_check.sv'. SBY 16:41:43 [insn_c_li_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_li.v' to 'insn_c_li_ch0/src/insn_c_li.v'. SBY 16:41:43 [insn_c_li_ch0] engine_0: smtbmc --nopresat boolector SBY 16:41:43 [insn_c_li_ch0] base: starting process "cd insn_c_li_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:41:43 [insn_c_jal_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:41:43 [insn_c_jal_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:41:43 [insn_c_jal_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:41:43 [insn_c_jal_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:41:43 [insn_c_jal_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:41:43 [insn_c_and_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:41:43 [insn_c_jal_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:41:43 [insn_c_jal_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:41:44 [insn_c_jal_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:41:44 [insn_c_jal_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:41:44 [insn_c_jal_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:41:44 [insn_c_jalr_ch0] base: finished (returncode=0) SBY 16:41:44 [insn_c_jalr_ch0] smt2: starting process "cd insn_c_jalr_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:41:44 [insn_c_jal_ch0] engine_0: ## 0:00:01 Skipping step 13.. SBY 16:41:44 [insn_c_jalr_ch0] smt2: finished (returncode=0) SBY 16:41:44 [insn_c_jalr_ch0] engine_0: starting process "cd insn_c_jalr_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:41:44 [insn_c_jal_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:41:44 [insn_c_jalr_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:41:44 [insn_c_jal_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:41:44 [insn_c_jalr_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:41:44 [insn_c_jal_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:41:44 [insn_c_jalr_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:41:45 [insn_c_jal_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:41:45 [insn_c_jalr_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:41:45 [insn_c_andi_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:41:45 [insn_c_jal_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:41:45 [insn_c_jalr_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:41:45 [insn_c_jal_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:41:45 [insn_c_jalr_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:41:45 [insn_c_jal_ch0] engine_0: ## 0:00:02 Checking assertions in step 20.. SBY 16:41:45 [insn_c_jalr_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:41:45 [insn_c_jr_ch0] base: finished (returncode=0) SBY 16:41:45 [insn_c_jr_ch0] smt2: starting process "cd insn_c_jr_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:41:45 [insn_c_jalr_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:41:45 [insn_c_jalr_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:41:45 [insn_c_jr_ch0] smt2: finished (returncode=0) SBY 16:41:45 [insn_c_jr_ch0] engine_0: starting process "cd insn_c_jr_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:41:45 [insn_c_jr_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:41:45 [insn_c_jalr_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:41:46 [insn_c_jr_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:41:46 [insn_c_jalr_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:41:46 [insn_c_jr_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:41:46 [insn_c_jalr_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:41:46 [insn_c_jr_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:41:46 [insn_c_jalr_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:41:46 [insn_c_jr_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:41:46 [insn_c_jalr_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:41:46 [insn_c_jr_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:41:46 [insn_c_jalr_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:41:46 [insn_c_jr_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:41:46 [insn_c_jalr_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:41:46 [insn_c_jr_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:41:46 [insn_c_jalr_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:41:47 [insn_c_jr_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:41:47 [insn_c_jalr_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:41:47 [insn_c_jr_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:41:47 [insn_c_jalr_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:41:47 [insn_c_jr_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:41:47 [insn_c_jalr_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:41:47 [insn_c_jr_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:41:47 [insn_c_jalr_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:41:47 [insn_c_jr_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:41:47 [insn_c_jalr_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:41:47 [insn_c_jr_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:41:47 [insn_c_jr_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:41:48 [insn_c_li_ch0] base: finished (returncode=0) SBY 16:41:48 [insn_c_li_ch0] smt2: starting process "cd insn_c_li_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:41:48 [insn_c_jr_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:41:48 [insn_c_li_ch0] smt2: finished (returncode=0) SBY 16:41:48 [insn_c_li_ch0] engine_0: starting process "cd insn_c_li_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:41:48 [insn_c_jr_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:41:48 [insn_c_li_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:41:48 [insn_c_jr_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:41:48 [insn_c_li_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:41:48 [insn_c_jr_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:41:48 [insn_c_li_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:41:48 [insn_c_jr_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:41:48 [insn_c_li_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:41:48 [insn_c_jr_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:41:48 [insn_c_li_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:41:48 [insn_c_jr_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:41:49 [insn_c_li_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:41:49 [insn_c_li_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:41:49 [insn_c_li_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:41:49 [insn_c_li_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:41:49 [insn_c_li_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:41:49 [insn_c_li_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:41:49 [insn_c_li_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:41:50 [insn_c_li_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:41:50 [insn_c_li_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:41:50 [insn_c_li_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:41:50 [insn_c_li_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:41:50 [insn_c_li_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:41:50 [insn_c_li_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:41:50 [insn_c_li_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:41:51 [insn_c_li_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:41:51 [insn_c_li_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:41:51 [insn_c_li_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:41:54 [insn_c_and_ch0] engine_0: ## 0:01:13 Status: passed SBY 16:41:54 [insn_c_and_ch0] engine_0: finished (returncode=0) SBY 16:41:54 [insn_c_and_ch0] engine_0: Status returned by engine: pass SBY 16:41:54 [insn_c_and_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:19 (79) SBY 16:41:54 [insn_c_and_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:19 (79) SBY 16:41:54 [insn_c_and_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:41:54 [insn_c_and_ch0] DONE (PASS, rc=0) sby insn_c_lui_ch0.sby SBY 16:41:54 [insn_c_lui_ch0] Writing 'insn_c_lui_ch0/src/defines.sv'. SBY 16:41:54 [insn_c_lui_ch0] Writing 'insn_c_lui_ch0/src/insn_c_lui_ch0.sv'. SBY 16:41:54 [insn_c_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_lui_ch0/src/rvfi_macros.vh'. SBY 16:41:54 [insn_c_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_lui_ch0/src/rvfi_channel.sv'. SBY 16:41:54 [insn_c_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_lui_ch0/src/rvfi_testbench.sv'. SBY 16:41:54 [insn_c_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_lui_ch0/src/rvfi_insn_check.sv'. SBY 16:41:54 [insn_c_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_lui.v' to 'insn_c_lui_ch0/src/insn_c_lui.v'. SBY 16:41:54 [insn_c_lui_ch0] engine_0: smtbmc --nopresat boolector SBY 16:41:54 [insn_c_lui_ch0] base: starting process "cd insn_c_lui_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:41:57 [insn_bge_ch0] engine_0: ## 0:02:52 Status: passed SBY 16:41:57 [insn_bge_ch0] engine_0: finished (returncode=0) SBY 16:41:57 [insn_bge_ch0] engine_0: Status returned by engine: pass SBY 16:41:57 [insn_bge_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:57 (177) SBY 16:41:57 [insn_bge_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:57 (177) SBY 16:41:57 [insn_bge_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:41:57 [insn_bge_ch0] DONE (PASS, rc=0) sby insn_c_lw_ch0.sby SBY 16:41:57 [insn_c_lw_ch0] Writing 'insn_c_lw_ch0/src/defines.sv'. SBY 16:41:57 [insn_c_lw_ch0] Writing 'insn_c_lw_ch0/src/insn_c_lw_ch0.sv'. SBY 16:41:57 [insn_c_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_lw_ch0/src/rvfi_macros.vh'. SBY 16:41:57 [insn_c_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_lw_ch0/src/rvfi_channel.sv'. SBY 16:41:57 [insn_c_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_lw_ch0/src/rvfi_testbench.sv'. SBY 16:41:57 [insn_c_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_lw_ch0/src/rvfi_insn_check.sv'. SBY 16:41:57 [insn_c_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_lw.v' to 'insn_c_lw_ch0/src/insn_c_lw.v'. SBY 16:41:57 [insn_c_lw_ch0] engine_0: smtbmc --nopresat boolector SBY 16:41:57 [insn_c_lw_ch0] base: starting process "cd insn_c_lw_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:41:58 [insn_c_beqz_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:41:59 [insn_c_lui_ch0] base: finished (returncode=0) SBY 16:41:59 [insn_c_lui_ch0] smt2: starting process "cd insn_c_lui_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:41:59 [insn_c_lui_ch0] smt2: finished (returncode=0) SBY 16:41:59 [insn_c_lui_ch0] engine_0: starting process "cd insn_c_lui_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:41:59 [insn_c_lui_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:00 [insn_c_lui_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:00 [insn_c_lui_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:00 [insn_c_lui_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:00 [insn_c_lui_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:00 [insn_c_lui_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:00 [insn_c_lui_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:00 [insn_c_lui_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:01 [insn_c_lui_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:01 [insn_c_lui_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:01 [insn_c_lui_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:01 [insn_c_lui_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:01 [insn_c_addi4spn_ch0] engine_0: ## 0:02:16 Status: passed SBY 16:42:01 [insn_c_addi4spn_ch0] engine_0: finished (returncode=0) SBY 16:42:01 [insn_c_addi4spn_ch0] engine_0: Status returned by engine: pass SBY 16:42:01 [insn_c_addi4spn_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:42:01 [insn_c_addi4spn_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:42:01 [insn_c_addi4spn_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:42:01 [insn_c_addi4spn_ch0] DONE (PASS, rc=0) sby insn_c_lwsp_ch0.sby SBY 16:42:01 [insn_c_lui_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:01 [insn_c_lwsp_ch0] Writing 'insn_c_lwsp_ch0/src/defines.sv'. SBY 16:42:01 [insn_c_lwsp_ch0] Writing 'insn_c_lwsp_ch0/src/insn_c_lwsp_ch0.sv'. SBY 16:42:01 [insn_c_lwsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_lwsp_ch0/src/rvfi_macros.vh'. SBY 16:42:01 [insn_c_lwsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_lwsp_ch0/src/rvfi_channel.sv'. SBY 16:42:01 [insn_c_lwsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_lwsp_ch0/src/rvfi_testbench.sv'. SBY 16:42:01 [insn_c_lwsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_lwsp_ch0/src/rvfi_insn_check.sv'. SBY 16:42:01 [insn_c_lwsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_lwsp.v' to 'insn_c_lwsp_ch0/src/insn_c_lwsp.v'. SBY 16:42:01 [insn_c_lwsp_ch0] engine_0: smtbmc --nopresat boolector SBY 16:42:01 [insn_c_lwsp_ch0] base: starting process "cd insn_c_lwsp_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:42:01 [insn_c_lui_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:42:01 [insn_c_lui_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:42:02 [insn_bltu_ch0] engine_0: ## 0:02:39 Status: passed SBY 16:42:02 [insn_c_lui_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:02 [insn_bltu_ch0] engine_0: finished (returncode=0) SBY 16:42:02 [insn_bltu_ch0] engine_0: Status returned by engine: pass SBY 16:42:02 [insn_bltu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:45 (165) SBY 16:42:02 [insn_bltu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:45 (165) SBY 16:42:02 [insn_bltu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:42:02 [insn_bltu_ch0] DONE (PASS, rc=0) sby insn_c_mv_ch0.sby SBY 16:42:02 [insn_c_mv_ch0] Writing 'insn_c_mv_ch0/src/defines.sv'. SBY 16:42:02 [insn_c_mv_ch0] Writing 'insn_c_mv_ch0/src/insn_c_mv_ch0.sv'. SBY 16:42:02 [insn_c_mv_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_mv_ch0/src/rvfi_macros.vh'. SBY 16:42:02 [insn_c_mv_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_mv_ch0/src/rvfi_channel.sv'. SBY 16:42:02 [insn_c_mv_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_mv_ch0/src/rvfi_testbench.sv'. SBY 16:42:02 [insn_c_mv_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_mv_ch0/src/rvfi_insn_check.sv'. SBY 16:42:02 [insn_c_mv_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_mv.v' to 'insn_c_mv_ch0/src/insn_c_mv.v'. SBY 16:42:02 [insn_c_mv_ch0] engine_0: smtbmc --nopresat boolector SBY 16:42:02 [insn_c_mv_ch0] base: starting process "cd insn_c_mv_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:42:02 [insn_c_lui_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:02 [insn_c_lui_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:02 [insn_c_lui_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:02 [insn_c_lui_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:02 [insn_c_lui_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:42:02 [insn_c_lui_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:42:03 [insn_c_lw_ch0] base: finished (returncode=0) SBY 16:42:03 [insn_c_lw_ch0] smt2: starting process "cd insn_c_lw_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:42:03 [insn_c_lw_ch0] smt2: finished (returncode=0) SBY 16:42:03 [insn_c_lw_ch0] engine_0: starting process "cd insn_c_lw_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:42:03 [insn_c_lw_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:03 [insn_c_lw_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:04 [insn_c_lw_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:04 [insn_c_andi_ch0] engine_0: ## 0:01:22 Status: passed SBY 16:42:04 [insn_c_lw_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:04 [insn_c_andi_ch0] engine_0: finished (returncode=0) SBY 16:42:04 [insn_c_andi_ch0] engine_0: Status returned by engine: pass SBY 16:42:04 [insn_c_andi_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:28 (88) SBY 16:42:04 [insn_c_andi_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:27 (87) SBY 16:42:04 [insn_c_andi_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:42:04 [insn_c_andi_ch0] DONE (PASS, rc=0) sby insn_c_or_ch0.sby SBY 16:42:04 [insn_c_or_ch0] Writing 'insn_c_or_ch0/src/defines.sv'. SBY 16:42:04 [insn_c_or_ch0] Writing 'insn_c_or_ch0/src/insn_c_or_ch0.sv'. SBY 16:42:04 [insn_c_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_or_ch0/src/rvfi_macros.vh'. SBY 16:42:04 [insn_c_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_or_ch0/src/rvfi_channel.sv'. SBY 16:42:04 [insn_c_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_or_ch0/src/rvfi_testbench.sv'. SBY 16:42:04 [insn_c_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_or_ch0/src/rvfi_insn_check.sv'. SBY 16:42:04 [insn_c_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_or.v' to 'insn_c_or_ch0/src/insn_c_or.v'. SBY 16:42:04 [insn_c_or_ch0] engine_0: smtbmc --nopresat boolector SBY 16:42:04 [insn_c_or_ch0] base: starting process "cd insn_c_or_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:42:04 [insn_c_lw_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:04 [insn_c_lw_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:04 [insn_c_lw_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:04 [insn_c_lw_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:04 [insn_c_lw_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:05 [insn_c_lw_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:05 [insn_c_lw_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:05 [insn_c_lw_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:05 [insn_c_lw_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:05 [insn_c_lw_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:42:05 [insn_c_lw_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:42:05 [insn_c_lw_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:06 [insn_c_lw_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:06 [insn_c_lw_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:06 [insn_c_lw_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:06 [insn_c_lw_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:06 [insn_c_lw_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:42:06 [insn_c_lw_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:42:07 [insn_c_lwsp_ch0] base: finished (returncode=0) SBY 16:42:07 [insn_c_lwsp_ch0] smt2: starting process "cd insn_c_lwsp_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:42:07 [insn_c_lwsp_ch0] smt2: finished (returncode=0) SBY 16:42:07 [insn_c_lwsp_ch0] engine_0: starting process "cd insn_c_lwsp_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:42:07 [insn_c_mv_ch0] base: finished (returncode=0) SBY 16:42:07 [insn_c_mv_ch0] smt2: starting process "cd insn_c_mv_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:42:07 [insn_c_lwsp_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:07 [insn_c_mv_ch0] smt2: finished (returncode=0) SBY 16:42:07 [insn_c_mv_ch0] engine_0: starting process "cd insn_c_mv_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:42:07 [insn_c_lwsp_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:07 [insn_c_mv_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:07 [insn_c_lwsp_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:07 [insn_c_mv_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:07 [insn_c_lwsp_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:07 [insn_c_mv_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:08 [insn_c_lwsp_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:08 [insn_c_mv_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:08 [insn_c_lwsp_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:08 [insn_c_mv_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:08 [insn_c_lwsp_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:08 [insn_c_mv_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:08 [insn_c_lwsp_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:08 [insn_c_mv_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:08 [insn_c_lwsp_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:08 [insn_c_mv_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:08 [insn_c_lwsp_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:08 [insn_c_mv_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:08 [insn_c_lwsp_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:08 [insn_c_mv_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:09 [insn_c_lwsp_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:09 [insn_c_mv_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:09 [insn_c_lwsp_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:09 [insn_c_mv_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:09 [insn_c_lwsp_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:42:09 [insn_c_mv_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:09 [insn_c_lwsp_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:42:09 [insn_c_mv_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:42:09 [insn_c_lwsp_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:09 [insn_c_mv_ch0] engine_0: ## 0:00:01 Skipping step 13.. SBY 16:42:09 [insn_c_or_ch0] base: finished (returncode=0) SBY 16:42:09 [insn_c_or_ch0] smt2: starting process "cd insn_c_or_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:42:09 [insn_c_lwsp_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:09 [insn_c_mv_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:09 [insn_c_or_ch0] smt2: finished (returncode=0) SBY 16:42:09 [insn_c_or_ch0] engine_0: starting process "cd insn_c_or_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:42:09 [insn_c_or_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:09 [insn_c_mv_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:09 [insn_c_lwsp_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:10 [insn_c_mv_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:10 [insn_c_lwsp_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:10 [insn_c_or_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:10 [insn_c_lwsp_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:10 [insn_c_mv_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:10 [insn_c_or_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:10 [insn_c_lwsp_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:42:10 [insn_c_or_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:10 [insn_c_mv_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:10 [insn_c_lwsp_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:42:10 [insn_c_or_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:10 [insn_c_mv_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:42:10 [insn_c_or_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:10 [insn_c_mv_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:42:10 [insn_c_or_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:10 [insn_c_or_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:11 [insn_c_or_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:11 [insn_c_or_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:11 [insn_c_or_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:11 [insn_c_or_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:11 [insn_c_or_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:11 [insn_c_or_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:42:11 [insn_c_or_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:42:12 [insn_c_or_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:12 [insn_c_or_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:12 [insn_c_or_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:12 [insn_c_or_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:12 [insn_c_or_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:12 [insn_c_or_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:42:13 [insn_c_or_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:42:15 [insn_bne_ch0] engine_0: ## 0:02:53 Status: passed SBY 16:42:15 [insn_bne_ch0] engine_0: finished (returncode=0) SBY 16:42:15 [insn_bne_ch0] engine_0: Status returned by engine: pass SBY 16:42:15 [insn_bne_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:59 (179) SBY 16:42:15 [insn_bne_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:58 (178) SBY 16:42:15 [insn_bne_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:42:15 [insn_bne_ch0] DONE (PASS, rc=0) sby insn_c_slli_ch0.sby SBY 16:42:16 [insn_c_slli_ch0] Writing 'insn_c_slli_ch0/src/defines.sv'. SBY 16:42:16 [insn_c_slli_ch0] Writing 'insn_c_slli_ch0/src/insn_c_slli_ch0.sv'. SBY 16:42:16 [insn_c_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_slli_ch0/src/rvfi_macros.vh'. SBY 16:42:16 [insn_c_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_slli_ch0/src/rvfi_channel.sv'. SBY 16:42:16 [insn_c_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_slli_ch0/src/rvfi_testbench.sv'. SBY 16:42:16 [insn_c_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_slli_ch0/src/rvfi_insn_check.sv'. SBY 16:42:16 [insn_c_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_slli.v' to 'insn_c_slli_ch0/src/insn_c_slli.v'. SBY 16:42:16 [insn_c_slli_ch0] engine_0: smtbmc --nopresat boolector SBY 16:42:16 [insn_c_slli_ch0] base: starting process "cd insn_c_slli_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:42:21 [insn_c_slli_ch0] base: finished (returncode=0) SBY 16:42:21 [insn_c_slli_ch0] smt2: starting process "cd insn_c_slli_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:42:22 [insn_c_slli_ch0] smt2: finished (returncode=0) SBY 16:42:22 [insn_c_slli_ch0] engine_0: starting process "cd insn_c_slli_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:42:22 [insn_c_slli_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:22 [insn_c_slli_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:22 [insn_c_slli_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:22 [insn_c_slli_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:22 [insn_c_slli_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:23 [insn_c_slli_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:23 [insn_c_slli_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:23 [insn_c_slli_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:23 [insn_c_slli_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:23 [insn_c_slli_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:23 [insn_c_slli_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:23 [insn_c_slli_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:24 [insn_c_slli_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:24 [insn_c_bnez_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:42:24 [insn_c_slli_ch0] engine_0: ## 0:00:02 Skipping step 12.. SBY 16:42:24 [insn_c_slli_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:42:24 [insn_c_slli_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:24 [insn_c_slli_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:24 [insn_c_slli_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:24 [insn_c_slli_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:25 [insn_c_slli_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:25 [insn_c_slli_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:42:25 [insn_c_slli_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:42:35 [insn_c_jr_ch0] engine_0: ## 0:00:49 Status: passed SBY 16:42:35 [insn_c_jr_ch0] engine_0: finished (returncode=0) SBY 16:42:35 [insn_c_jr_ch0] engine_0: Status returned by engine: pass SBY 16:42:35 [insn_c_jr_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:54 (54) SBY 16:42:35 [insn_c_jr_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:54 (54) SBY 16:42:35 [insn_c_jr_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:42:35 [insn_c_jr_ch0] DONE (PASS, rc=0) sby insn_c_srai_ch0.sby SBY 16:42:35 [insn_c_srai_ch0] Writing 'insn_c_srai_ch0/src/defines.sv'. SBY 16:42:35 [insn_c_srai_ch0] Writing 'insn_c_srai_ch0/src/insn_c_srai_ch0.sv'. SBY 16:42:35 [insn_c_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_srai_ch0/src/rvfi_macros.vh'. SBY 16:42:35 [insn_c_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_srai_ch0/src/rvfi_channel.sv'. SBY 16:42:35 [insn_c_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_srai_ch0/src/rvfi_testbench.sv'. SBY 16:42:35 [insn_c_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_srai_ch0/src/rvfi_insn_check.sv'. SBY 16:42:35 [insn_c_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_srai.v' to 'insn_c_srai_ch0/src/insn_c_srai.v'. SBY 16:42:35 [insn_c_srai_ch0] engine_0: smtbmc --nopresat boolector SBY 16:42:35 [insn_c_srai_ch0] base: starting process "cd insn_c_srai_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:42:38 [insn_c_j_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:42:40 [insn_c_srai_ch0] base: finished (returncode=0) SBY 16:42:40 [insn_c_srai_ch0] smt2: starting process "cd insn_c_srai_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:42:41 [insn_c_srai_ch0] smt2: finished (returncode=0) SBY 16:42:41 [insn_c_srai_ch0] engine_0: starting process "cd insn_c_srai_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:42:41 [insn_c_srai_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:41 [insn_c_srai_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:41 [insn_c_srai_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:41 [insn_c_srai_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:41 [insn_c_srai_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:41 [insn_c_srai_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:42 [insn_c_srai_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:42 [insn_c_srai_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:42 [insn_c_srai_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:42 [insn_c_srai_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:42 [insn_c_srai_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:42 [insn_c_srai_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:43 [insn_c_srai_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:43 [insn_c_srai_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:42:43 [insn_c_srai_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:42:43 [insn_c_srai_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:43 [insn_c_srai_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:43 [insn_c_srai_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:43 [insn_c_srai_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:44 [insn_c_srai_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:44 [insn_c_srai_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:42:44 [insn_c_srai_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:42:45 [insn_c_jal_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:42:46 [insn_bgeu_ch0] engine_0: ## 0:03:28 Status: passed SBY 16:42:46 [insn_bgeu_ch0] engine_0: finished (returncode=0) SBY 16:42:46 [insn_bgeu_ch0] engine_0: Status returned by engine: pass SBY 16:42:46 [insn_bgeu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:03:34 (214) SBY 16:42:46 [insn_bgeu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:03:34 (214) SBY 16:42:46 [insn_bgeu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:42:46 [insn_bgeu_ch0] DONE (PASS, rc=0) sby insn_c_srli_ch0.sby SBY 16:42:46 [insn_c_srli_ch0] Writing 'insn_c_srli_ch0/src/defines.sv'. SBY 16:42:46 [insn_c_srli_ch0] Writing 'insn_c_srli_ch0/src/insn_c_srli_ch0.sv'. SBY 16:42:46 [insn_c_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_srli_ch0/src/rvfi_macros.vh'. SBY 16:42:46 [insn_c_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_srli_ch0/src/rvfi_channel.sv'. SBY 16:42:46 [insn_c_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_srli_ch0/src/rvfi_testbench.sv'. SBY 16:42:46 [insn_c_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_srli_ch0/src/rvfi_insn_check.sv'. SBY 16:42:46 [insn_c_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_srli.v' to 'insn_c_srli_ch0/src/insn_c_srli.v'. SBY 16:42:46 [insn_c_srli_ch0] engine_0: smtbmc --nopresat boolector SBY 16:42:46 [insn_c_srli_ch0] base: starting process "cd insn_c_srli_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:42:46 [insn_c_jalr_ch0] engine_0: ## 0:01:02 Status: passed SBY 16:42:46 [insn_c_jalr_ch0] engine_0: finished (returncode=0) SBY 16:42:46 [insn_c_jalr_ch0] engine_0: Status returned by engine: pass SBY 16:42:46 [insn_c_jalr_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:07 (67) SBY 16:42:46 [insn_c_jalr_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:07 (67) SBY 16:42:46 [insn_c_jalr_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:42:46 [insn_c_jalr_ch0] DONE (PASS, rc=0) sby insn_c_sub_ch0.sby SBY 16:42:47 [insn_c_sub_ch0] Writing 'insn_c_sub_ch0/src/defines.sv'. SBY 16:42:47 [insn_c_sub_ch0] Writing 'insn_c_sub_ch0/src/insn_c_sub_ch0.sv'. SBY 16:42:47 [insn_c_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_sub_ch0/src/rvfi_macros.vh'. SBY 16:42:47 [insn_c_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_sub_ch0/src/rvfi_channel.sv'. SBY 16:42:47 [insn_c_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_sub_ch0/src/rvfi_testbench.sv'. SBY 16:42:47 [insn_c_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_sub_ch0/src/rvfi_insn_check.sv'. SBY 16:42:47 [insn_c_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_sub.v' to 'insn_c_sub_ch0/src/insn_c_sub.v'. SBY 16:42:47 [insn_c_sub_ch0] engine_0: smtbmc --nopresat boolector SBY 16:42:47 [insn_c_sub_ch0] base: starting process "cd insn_c_sub_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:42:51 [insn_c_li_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:42:52 [insn_c_srli_ch0] base: finished (returncode=0) SBY 16:42:52 [insn_c_srli_ch0] smt2: starting process "cd insn_c_srli_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:42:52 [insn_c_srli_ch0] smt2: finished (returncode=0) SBY 16:42:52 [insn_c_srli_ch0] engine_0: starting process "cd insn_c_srli_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:42:52 [insn_c_srli_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:52 [insn_c_sub_ch0] base: finished (returncode=0) SBY 16:42:52 [insn_c_sub_ch0] smt2: starting process "cd insn_c_sub_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:42:52 [insn_c_srli_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:52 [insn_c_sub_ch0] smt2: finished (returncode=0) SBY 16:42:52 [insn_c_sub_ch0] engine_0: starting process "cd insn_c_sub_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:42:52 [insn_c_sub_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:42:52 [insn_c_srli_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:52 [insn_c_sub_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:42:52 [insn_c_srli_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:53 [insn_c_sub_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:42:53 [insn_c_srli_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:53 [insn_c_sub_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:42:53 [insn_c_srli_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:53 [insn_c_sub_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:42:53 [insn_c_srli_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:53 [insn_c_sub_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:42:53 [insn_c_srli_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:53 [insn_c_sub_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:42:53 [insn_c_srli_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:53 [insn_c_sub_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:42:53 [insn_c_srli_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:53 [insn_c_sub_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:42:53 [insn_c_srli_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:54 [insn_c_sub_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:42:54 [insn_c_srli_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:54 [insn_c_sub_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:42:54 [insn_c_srli_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:54 [insn_c_sub_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:42:54 [insn_c_srli_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:42:54 [insn_c_sub_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:42:54 [insn_c_srli_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:42:54 [insn_c_sub_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:42:54 [insn_c_srli_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:54 [insn_c_sub_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:42:54 [insn_c_srli_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:54 [insn_c_sub_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:42:55 [insn_c_srli_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:55 [insn_c_sub_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:42:55 [insn_c_srli_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:55 [insn_c_sub_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:42:55 [insn_c_srli_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:55 [insn_c_sub_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:42:55 [insn_c_srli_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:42:55 [insn_c_sub_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:42:55 [insn_c_srli_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:42:55 [insn_c_sub_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:42:55 [insn_c_sub_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:43:03 [insn_c_lui_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:07 [insn_c_lw_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:10 [insn_c_lwsp_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:10 [insn_c_mv_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:11 [insn_c_li_ch0] engine_0: ## 0:01:23 Status: passed SBY 16:43:11 [insn_c_li_ch0] engine_0: finished (returncode=0) SBY 16:43:11 [insn_c_li_ch0] engine_0: Status returned by engine: pass SBY 16:43:11 [insn_c_li_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:28 (88) SBY 16:43:11 [insn_c_li_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:28 (88) SBY 16:43:11 [insn_c_li_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:43:11 [insn_c_li_ch0] DONE (PASS, rc=0) sby insn_c_sw_ch0.sby SBY 16:43:11 [insn_c_sw_ch0] Writing 'insn_c_sw_ch0/src/defines.sv'. SBY 16:43:11 [insn_c_sw_ch0] Writing 'insn_c_sw_ch0/src/insn_c_sw_ch0.sv'. SBY 16:43:11 [insn_c_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_sw_ch0/src/rvfi_macros.vh'. SBY 16:43:11 [insn_c_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_sw_ch0/src/rvfi_channel.sv'. SBY 16:43:11 [insn_c_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_sw_ch0/src/rvfi_testbench.sv'. SBY 16:43:11 [insn_c_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_sw_ch0/src/rvfi_insn_check.sv'. SBY 16:43:11 [insn_c_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_sw.v' to 'insn_c_sw_ch0/src/insn_c_sw.v'. SBY 16:43:11 [insn_c_sw_ch0] engine_0: smtbmc --nopresat boolector SBY 16:43:11 [insn_c_sw_ch0] base: starting process "cd insn_c_sw_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:43:13 [insn_c_or_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:15 [insn_c_lui_ch0] engine_0: ## 0:01:15 Status: passed SBY 16:43:15 [insn_c_lui_ch0] engine_0: finished (returncode=0) SBY 16:43:15 [insn_c_lui_ch0] engine_0: Status returned by engine: pass SBY 16:43:15 [insn_c_lui_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:20 (80) SBY 16:43:15 [insn_c_lui_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:20 (80) SBY 16:43:15 [insn_c_lui_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:43:15 [insn_c_lui_ch0] DONE (PASS, rc=0) sby insn_c_swsp_ch0.sby SBY 16:43:15 [insn_c_swsp_ch0] Writing 'insn_c_swsp_ch0/src/defines.sv'. SBY 16:43:15 [insn_c_swsp_ch0] Writing 'insn_c_swsp_ch0/src/insn_c_swsp_ch0.sv'. SBY 16:43:15 [insn_c_swsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_swsp_ch0/src/rvfi_macros.vh'. SBY 16:43:15 [insn_c_swsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_swsp_ch0/src/rvfi_channel.sv'. SBY 16:43:15 [insn_c_swsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_swsp_ch0/src/rvfi_testbench.sv'. SBY 16:43:15 [insn_c_swsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_swsp_ch0/src/rvfi_insn_check.sv'. SBY 16:43:15 [insn_c_swsp_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_swsp.v' to 'insn_c_swsp_ch0/src/insn_c_swsp.v'. SBY 16:43:15 [insn_c_swsp_ch0] engine_0: smtbmc --nopresat boolector SBY 16:43:15 [insn_c_swsp_ch0] base: starting process "cd insn_c_swsp_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:43:17 [insn_c_sw_ch0] base: finished (returncode=0) SBY 16:43:17 [insn_c_sw_ch0] smt2: starting process "cd insn_c_sw_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:43:17 [insn_c_sw_ch0] smt2: finished (returncode=0) SBY 16:43:17 [insn_c_sw_ch0] engine_0: starting process "cd insn_c_sw_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:43:18 [insn_c_sw_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:43:18 [insn_c_sw_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:43:18 [insn_c_sw_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:43:18 [insn_c_sw_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:43:18 [insn_c_sw_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:43:18 [insn_c_sw_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:43:18 [insn_c_sw_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:43:19 [insn_c_sw_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:43:19 [insn_c_sw_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:43:19 [insn_c_sw_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:43:19 [insn_c_sw_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:43:19 [insn_c_sw_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:43:19 [insn_c_sw_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:43:20 [insn_c_sw_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:43:20 [insn_c_sw_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:43:20 [insn_c_sw_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:43:20 [insn_c_sw_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:43:20 [insn_c_sw_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:43:20 [insn_c_sw_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:43:20 [insn_c_sw_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:43:21 [insn_c_swsp_ch0] base: finished (returncode=0) SBY 16:43:21 [insn_c_swsp_ch0] smt2: starting process "cd insn_c_swsp_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:43:21 [insn_c_sw_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:43:21 [insn_c_sw_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:43:21 [insn_c_swsp_ch0] smt2: finished (returncode=0) SBY 16:43:21 [insn_c_swsp_ch0] engine_0: starting process "cd insn_c_swsp_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:43:21 [insn_c_swsp_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:43:21 [insn_c_swsp_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:43:21 [insn_c_swsp_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:43:21 [insn_c_swsp_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:43:21 [insn_c_swsp_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:43:22 [insn_c_swsp_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:43:22 [insn_c_swsp_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:43:22 [insn_c_swsp_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:43:22 [insn_c_swsp_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:43:22 [insn_c_swsp_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:43:22 [insn_c_swsp_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:43:22 [insn_blt_ch0] engine_0: ## 0:04:00 Status: passed SBY 16:43:22 [insn_blt_ch0] engine_0: finished (returncode=0) SBY 16:43:22 [insn_blt_ch0] engine_0: Status returned by engine: pass SBY 16:43:22 [insn_blt_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:04:06 (246) SBY 16:43:22 [insn_blt_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:04:05 (245) SBY 16:43:22 [insn_blt_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:43:22 [insn_blt_ch0] DONE (PASS, rc=0) sby insn_c_xor_ch0.sby SBY 16:43:22 [insn_c_xor_ch0] Writing 'insn_c_xor_ch0/src/defines.sv'. SBY 16:43:22 [insn_c_xor_ch0] Writing 'insn_c_xor_ch0/src/insn_c_xor_ch0.sv'. SBY 16:43:22 [insn_c_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_c_xor_ch0/src/rvfi_macros.vh'. SBY 16:43:22 [insn_c_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_c_xor_ch0/src/rvfi_channel.sv'. SBY 16:43:22 [insn_c_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_c_xor_ch0/src/rvfi_testbench.sv'. SBY 16:43:22 [insn_c_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_c_xor_ch0/src/rvfi_insn_check.sv'. SBY 16:43:22 [insn_c_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_c_xor.v' to 'insn_c_xor_ch0/src/insn_c_xor.v'. SBY 16:43:22 [insn_c_xor_ch0] engine_0: smtbmc --nopresat boolector SBY 16:43:22 [insn_c_xor_ch0] base: starting process "cd insn_c_xor_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:43:22 [insn_c_swsp_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:43:23 [insn_c_swsp_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:43:23 [insn_c_swsp_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:43:23 [insn_c_swsp_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:43:23 [insn_c_swsp_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:43:23 [insn_c_swsp_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:43:23 [insn_c_swsp_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:43:23 [insn_c_swsp_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:43:24 [insn_c_swsp_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:43:24 [insn_c_swsp_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:43:24 [insn_c_swsp_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:43:25 [insn_c_slli_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:27 [insn_c_beqz_ch0] engine_0: ## 0:02:32 Status: passed SBY 16:43:27 [insn_c_beqz_ch0] engine_0: finished (returncode=0) SBY 16:43:27 [insn_c_beqz_ch0] engine_0: Status returned by engine: pass SBY 16:43:27 [insn_c_beqz_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:38 (158) SBY 16:43:27 [insn_c_beqz_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:38 (158) SBY 16:43:27 [insn_c_beqz_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:43:27 [insn_c_beqz_ch0] DONE (PASS, rc=0) sby insn_div_ch0.sby SBY 16:43:27 [insn_div_ch0] Writing 'insn_div_ch0/src/defines.sv'. SBY 16:43:27 [insn_div_ch0] Writing 'insn_div_ch0/src/insn_div_ch0.sv'. SBY 16:43:27 [insn_div_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_div_ch0/src/rvfi_macros.vh'. SBY 16:43:27 [insn_div_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_div_ch0/src/rvfi_channel.sv'. SBY 16:43:27 [insn_div_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_div_ch0/src/rvfi_testbench.sv'. SBY 16:43:27 [insn_div_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_div_ch0/src/rvfi_insn_check.sv'. SBY 16:43:27 [insn_div_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_div.v' to 'insn_div_ch0/src/insn_div.v'. SBY 16:43:27 [insn_div_ch0] engine_0: smtbmc --nopresat boolector SBY 16:43:27 [insn_div_ch0] base: starting process "cd insn_div_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:43:28 [insn_c_xor_ch0] base: finished (returncode=0) SBY 16:43:28 [insn_c_xor_ch0] smt2: starting process "cd insn_c_xor_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:43:28 [insn_c_xor_ch0] smt2: finished (returncode=0) SBY 16:43:28 [insn_c_xor_ch0] engine_0: starting process "cd insn_c_xor_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:43:28 [insn_c_xor_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:43:28 [insn_c_xor_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:43:29 [insn_c_xor_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:43:29 [insn_c_xor_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:43:29 [insn_c_xor_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:43:29 [insn_c_xor_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:43:29 [insn_c_xor_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:43:29 [insn_c_xor_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:43:29 [insn_c_xor_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:43:30 [insn_c_xor_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:43:30 [insn_c_xor_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:43:30 [insn_c_xor_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:43:30 [insn_c_xor_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:43:30 [insn_c_xor_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:43:30 [insn_c_xor_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:43:30 [insn_c_xor_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:43:31 [insn_c_xor_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:43:31 [insn_c_xor_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:43:31 [insn_c_or_ch0] engine_0: ## 0:01:21 Status: passed SBY 16:43:31 [insn_c_xor_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:43:31 [insn_c_or_ch0] engine_0: finished (returncode=0) SBY 16:43:31 [insn_c_or_ch0] engine_0: Status returned by engine: pass SBY 16:43:31 [insn_c_or_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:27 (87) SBY 16:43:31 [insn_c_or_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:26 (86) SBY 16:43:31 [insn_c_or_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:43:31 [insn_c_or_ch0] DONE (PASS, rc=0) sby insn_divu_ch0.sby SBY 16:43:31 [insn_divu_ch0] Writing 'insn_divu_ch0/src/defines.sv'. SBY 16:43:31 [insn_divu_ch0] Writing 'insn_divu_ch0/src/insn_divu_ch0.sv'. SBY 16:43:31 [insn_divu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_divu_ch0/src/rvfi_macros.vh'. SBY 16:43:31 [insn_divu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_divu_ch0/src/rvfi_channel.sv'. SBY 16:43:31 [insn_divu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_divu_ch0/src/rvfi_testbench.sv'. SBY 16:43:31 [insn_divu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_divu_ch0/src/rvfi_insn_check.sv'. SBY 16:43:31 [insn_divu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_divu.v' to 'insn_divu_ch0/src/insn_divu.v'. SBY 16:43:31 [insn_divu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:43:31 [insn_divu_ch0] base: starting process "cd insn_divu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:43:31 [insn_c_xor_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:43:31 [insn_c_xor_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:43:31 [insn_c_xor_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:43:32 [insn_div_ch0] base: finished (returncode=0) SBY 16:43:32 [insn_div_ch0] smt2: starting process "cd insn_div_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:43:32 [insn_div_ch0] smt2: finished (returncode=0) SBY 16:43:32 [insn_div_ch0] engine_0: starting process "cd insn_div_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:43:32 [insn_div_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:43:33 [insn_div_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:43:33 [insn_div_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:43:33 [insn_div_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:43:33 [insn_div_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:43:33 [insn_div_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:43:33 [insn_div_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:43:34 [insn_div_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:43:34 [insn_div_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:43:34 [insn_div_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:43:34 [insn_div_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:43:34 [insn_div_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:43:34 [insn_div_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:43:34 [insn_div_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:43:35 [insn_div_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:43:35 [insn_div_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:43:35 [insn_div_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:43:35 [insn_div_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:43:35 [insn_div_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:43:35 [insn_div_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:43:35 [insn_div_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:43:36 [insn_div_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:43:36 [insn_divu_ch0] base: finished (returncode=0) SBY 16:43:36 [insn_divu_ch0] smt2: starting process "cd insn_divu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:43:36 [insn_divu_ch0] smt2: finished (returncode=0) SBY 16:43:36 [insn_divu_ch0] engine_0: starting process "cd insn_divu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:43:36 [insn_divu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:43:37 [insn_divu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:43:37 [insn_c_mv_ch0] engine_0: ## 0:01:29 Status: passed SBY 16:43:37 [insn_c_mv_ch0] engine_0: finished (returncode=0) SBY 16:43:37 [insn_c_mv_ch0] engine_0: Status returned by engine: pass SBY 16:43:37 [insn_c_mv_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:35 (95) SBY 16:43:37 [insn_c_mv_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:34 (94) SBY 16:43:37 [insn_c_mv_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:43:37 [insn_c_mv_ch0] DONE (PASS, rc=0) sby insn_jal_ch0.sby SBY 16:43:37 [insn_divu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:43:37 [insn_jal_ch0] Writing 'insn_jal_ch0/src/defines.sv'. SBY 16:43:37 [insn_jal_ch0] Writing 'insn_jal_ch0/src/insn_jal_ch0.sv'. SBY 16:43:37 [insn_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_jal_ch0/src/rvfi_macros.vh'. SBY 16:43:37 [insn_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_jal_ch0/src/rvfi_channel.sv'. SBY 16:43:37 [insn_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_jal_ch0/src/rvfi_testbench.sv'. SBY 16:43:37 [insn_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_jal_ch0/src/rvfi_insn_check.sv'. SBY 16:43:37 [insn_jal_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_jal.v' to 'insn_jal_ch0/src/insn_jal.v'. SBY 16:43:37 [insn_jal_ch0] engine_0: smtbmc --nopresat boolector SBY 16:43:37 [insn_jal_ch0] base: starting process "cd insn_jal_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:43:37 [insn_divu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:43:37 [insn_divu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:43:37 [insn_divu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:43:37 [insn_divu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:43:38 [insn_divu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:43:38 [insn_divu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:43:38 [insn_divu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:43:38 [insn_divu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:43:38 [insn_divu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:43:38 [insn_divu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:43:38 [insn_divu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:43:39 [insn_divu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:43:39 [insn_divu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:43:39 [insn_divu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:43:39 [insn_divu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:43:39 [insn_divu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:43:39 [insn_divu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:43:39 [insn_divu_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:43:40 [insn_divu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:43:40 [insn_c_j_ch0] engine_0: ## 0:02:05 Status: passed SBY 16:43:40 [insn_c_j_ch0] engine_0: finished (returncode=0) SBY 16:43:40 [insn_c_j_ch0] engine_0: Status returned by engine: pass SBY 16:43:40 [insn_c_j_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:11 (131) SBY 16:43:40 [insn_c_j_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:10 (130) SBY 16:43:40 [insn_c_j_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:43:40 [insn_c_j_ch0] DONE (PASS, rc=0) sby insn_jalr_ch0.sby SBY 16:43:40 [insn_jalr_ch0] Writing 'insn_jalr_ch0/src/defines.sv'. SBY 16:43:40 [insn_jalr_ch0] Writing 'insn_jalr_ch0/src/insn_jalr_ch0.sv'. SBY 16:43:40 [insn_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_jalr_ch0/src/rvfi_macros.vh'. SBY 16:43:40 [insn_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_jalr_ch0/src/rvfi_channel.sv'. SBY 16:43:40 [insn_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_jalr_ch0/src/rvfi_testbench.sv'. SBY 16:43:40 [insn_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_jalr_ch0/src/rvfi_insn_check.sv'. SBY 16:43:40 [insn_jalr_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_jalr.v' to 'insn_jalr_ch0/src/insn_jalr.v'. SBY 16:43:40 [insn_jalr_ch0] engine_0: smtbmc --nopresat boolector SBY 16:43:40 [insn_jalr_ch0] base: starting process "cd insn_jalr_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:43:42 [insn_jal_ch0] base: finished (returncode=0) SBY 16:43:42 [insn_jal_ch0] smt2: starting process "cd insn_jal_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:43:42 [insn_jal_ch0] smt2: finished (returncode=0) SBY 16:43:42 [insn_jal_ch0] engine_0: starting process "cd insn_jal_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:43:42 [insn_jal_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:43:42 [insn_jal_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:43:43 [insn_jal_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:43:43 [insn_jal_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:43:43 [insn_jal_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:43:43 [insn_jal_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:43:43 [insn_jal_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:43:43 [insn_jal_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:43:43 [insn_jal_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:43:44 [insn_jal_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:43:44 [insn_jal_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:43:44 [insn_jal_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:43:44 [insn_jal_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:43:44 [insn_c_srai_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:44 [insn_jal_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:43:44 [insn_jal_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:43:45 [insn_jal_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:43:45 [insn_jal_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:43:45 [insn_jal_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:43:45 [insn_jal_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:43:45 [insn_jalr_ch0] base: finished (returncode=0) SBY 16:43:45 [insn_jalr_ch0] smt2: starting process "cd insn_jalr_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:43:45 [insn_jal_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:43:45 [insn_jalr_ch0] smt2: finished (returncode=0) SBY 16:43:45 [insn_jalr_ch0] engine_0: starting process "cd insn_jalr_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:43:45 [insn_jal_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:43:45 [insn_jalr_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:43:45 [insn_jal_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:43:45 [insn_jalr_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:43:46 [insn_jalr_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:43:46 [insn_jalr_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:43:46 [insn_jalr_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:43:46 [insn_jalr_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:43:46 [insn_jalr_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:43:46 [insn_jalr_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:43:47 [insn_jalr_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:43:47 [insn_jalr_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:43:47 [insn_jalr_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:43:47 [insn_jalr_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:43:47 [insn_jalr_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:43:47 [insn_jalr_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:43:47 [insn_jalr_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:43:48 [insn_jalr_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:43:48 [insn_jalr_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:43:48 [insn_jalr_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:43:48 [insn_jalr_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:43:48 [insn_jalr_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:43:48 [insn_jalr_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:43:48 [insn_jalr_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:43:51 [insn_c_bnez_ch0] engine_0: ## 0:02:30 Status: passed SBY 16:43:51 [insn_c_bnez_ch0] engine_0: finished (returncode=0) SBY 16:43:51 [insn_c_bnez_ch0] engine_0: Status returned by engine: pass SBY 16:43:51 [insn_c_bnez_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:36 (156) SBY 16:43:51 [insn_c_bnez_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:36 (156) SBY 16:43:51 [insn_c_bnez_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:43:51 [insn_c_bnez_ch0] DONE (PASS, rc=0) sby insn_lb_ch0.sby SBY 16:43:51 [insn_lb_ch0] Writing 'insn_lb_ch0/src/defines.sv'. SBY 16:43:51 [insn_lb_ch0] Writing 'insn_lb_ch0/src/insn_lb_ch0.sv'. SBY 16:43:51 [insn_lb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_lb_ch0/src/rvfi_macros.vh'. SBY 16:43:51 [insn_lb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_lb_ch0/src/rvfi_channel.sv'. SBY 16:43:51 [insn_lb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_lb_ch0/src/rvfi_testbench.sv'. SBY 16:43:51 [insn_lb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_lb_ch0/src/rvfi_insn_check.sv'. SBY 16:43:51 [insn_lb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_lb.v' to 'insn_lb_ch0/src/insn_lb.v'. SBY 16:43:51 [insn_lb_ch0] engine_0: smtbmc --nopresat boolector SBY 16:43:51 [insn_lb_ch0] base: starting process "cd insn_lb_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:43:55 [insn_c_srli_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:56 [insn_c_sub_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:43:57 [insn_lb_ch0] base: finished (returncode=0) SBY 16:43:57 [insn_lb_ch0] smt2: starting process "cd insn_lb_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:43:57 [insn_lb_ch0] smt2: finished (returncode=0) SBY 16:43:57 [insn_lb_ch0] engine_0: starting process "cd insn_lb_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:43:58 [insn_lb_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:43:58 [insn_lb_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:43:58 [insn_lb_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:43:58 [insn_lb_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:43:58 [insn_lb_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:43:58 [insn_lb_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:43:58 [insn_lb_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:43:59 [insn_lb_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:43:59 [insn_lb_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:43:59 [insn_lb_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:43:59 [insn_lb_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:43:59 [insn_lb_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:43:59 [insn_lb_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:43:59 [insn_lb_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:44:00 [insn_c_jal_ch0] engine_0: ## 0:02:17 Status: passed SBY 16:44:00 [insn_c_jal_ch0] engine_0: finished (returncode=0) SBY 16:44:00 [insn_c_jal_ch0] engine_0: Status returned by engine: pass SBY 16:44:00 [insn_c_jal_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:44:00 [insn_c_jal_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:44:00 [insn_c_jal_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:44:00 [insn_c_jal_ch0] DONE (PASS, rc=0) SBY 16:44:00 [insn_lb_ch0] engine_0: ## 0:00:02 Skipping step 13.. sby insn_lbu_ch0.sby SBY 16:44:00 [insn_lbu_ch0] Writing 'insn_lbu_ch0/src/defines.sv'. SBY 16:44:00 [insn_lbu_ch0] Writing 'insn_lbu_ch0/src/insn_lbu_ch0.sv'. SBY 16:44:00 [insn_lbu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_lbu_ch0/src/rvfi_macros.vh'. SBY 16:44:00 [insn_lbu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_lbu_ch0/src/rvfi_channel.sv'. SBY 16:44:00 [insn_lbu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_lbu_ch0/src/rvfi_testbench.sv'. SBY 16:44:00 [insn_lbu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_lbu_ch0/src/rvfi_insn_check.sv'. SBY 16:44:00 [insn_lbu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_lbu.v' to 'insn_lbu_ch0/src/insn_lbu.v'. SBY 16:44:00 [insn_lbu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:44:00 [insn_lbu_ch0] base: starting process "cd insn_lbu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:44:00 [insn_lb_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:44:00 [insn_lb_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:44:00 [insn_lb_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:44:00 [insn_lb_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:44:00 [insn_lb_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:44:01 [insn_lb_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:44:01 [insn_lb_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:44:05 [insn_c_lwsp_ch0] engine_0: ## 0:01:58 Status: passed SBY 16:44:05 [insn_c_lwsp_ch0] engine_0: finished (returncode=0) SBY 16:44:05 [insn_c_lwsp_ch0] engine_0: Status returned by engine: pass SBY 16:44:05 [insn_c_lwsp_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:03 (123) SBY 16:44:05 [insn_c_lwsp_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:03 (123) SBY 16:44:05 [insn_c_lwsp_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:44:05 [insn_c_lwsp_ch0] DONE (PASS, rc=0) sby insn_lh_ch0.sby SBY 16:44:05 [insn_lh_ch0] Writing 'insn_lh_ch0/src/defines.sv'. SBY 16:44:05 [insn_lh_ch0] Writing 'insn_lh_ch0/src/insn_lh_ch0.sv'. SBY 16:44:05 [insn_lh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_lh_ch0/src/rvfi_macros.vh'. SBY 16:44:05 [insn_lh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_lh_ch0/src/rvfi_channel.sv'. SBY 16:44:05 [insn_lh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_lh_ch0/src/rvfi_testbench.sv'. SBY 16:44:05 [insn_lh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_lh_ch0/src/rvfi_insn_check.sv'. SBY 16:44:05 [insn_lh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_lh.v' to 'insn_lh_ch0/src/insn_lh.v'. SBY 16:44:05 [insn_lh_ch0] engine_0: smtbmc --nopresat boolector SBY 16:44:05 [insn_lh_ch0] base: starting process "cd insn_lh_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:44:05 [insn_lbu_ch0] base: finished (returncode=0) SBY 16:44:05 [insn_lbu_ch0] smt2: starting process "cd insn_lbu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:44:06 [insn_lbu_ch0] smt2: finished (returncode=0) SBY 16:44:06 [insn_lbu_ch0] engine_0: starting process "cd insn_lbu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:44:06 [insn_lbu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:44:06 [insn_lbu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:44:06 [insn_lbu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:44:06 [insn_lbu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:44:06 [insn_lbu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:44:07 [insn_lbu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:44:07 [insn_lbu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:44:07 [insn_lbu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:44:07 [insn_lbu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:44:07 [insn_lbu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:44:07 [insn_lbu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:44:07 [insn_lbu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:44:08 [insn_lbu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:44:08 [insn_lbu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:44:08 [insn_lbu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:44:08 [insn_lbu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:44:08 [insn_lbu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:44:08 [insn_lbu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:44:08 [reg_ch0] engine_0: ## 0:05:04 waiting for solver (5 minutes) SBY 16:44:08 [insn_lbu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:44:09 [insn_lbu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:44:09 [insn_lbu_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:44:09 [insn_lbu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:44:10 [insn_c_lw_ch0] engine_0: ## 0:02:06 Status: passed SBY 16:44:10 [insn_c_lw_ch0] engine_0: finished (returncode=0) SBY 16:44:10 [insn_c_lw_ch0] engine_0: Status returned by engine: pass SBY 16:44:10 [insn_c_lw_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:12 (132) SBY 16:44:10 [insn_c_lw_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:12 (132) SBY 16:44:10 [insn_c_lw_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:44:10 [insn_c_lw_ch0] DONE (PASS, rc=0) sby insn_lhu_ch0.sby SBY 16:44:10 [insn_lhu_ch0] Writing 'insn_lhu_ch0/src/defines.sv'. SBY 16:44:10 [insn_lhu_ch0] Writing 'insn_lhu_ch0/src/insn_lhu_ch0.sv'. SBY 16:44:10 [insn_lhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_lhu_ch0/src/rvfi_macros.vh'. SBY 16:44:10 [insn_lhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_lhu_ch0/src/rvfi_channel.sv'. SBY 16:44:10 [insn_lhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_lhu_ch0/src/rvfi_testbench.sv'. SBY 16:44:10 [insn_lhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_lhu_ch0/src/rvfi_insn_check.sv'. SBY 16:44:10 [insn_lhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_lhu.v' to 'insn_lhu_ch0/src/insn_lhu.v'. SBY 16:44:10 [insn_lhu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:44:10 [insn_lhu_ch0] base: starting process "cd insn_lhu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:44:11 [insn_lh_ch0] base: finished (returncode=0) SBY 16:44:11 [insn_lh_ch0] smt2: starting process "cd insn_lh_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:44:11 [insn_lh_ch0] smt2: finished (returncode=0) SBY 16:44:11 [insn_lh_ch0] engine_0: starting process "cd insn_lh_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:44:11 [insn_lh_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:44:11 [insn_lh_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:44:12 [insn_lh_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:44:12 [insn_lh_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:44:12 [insn_lh_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:44:12 [insn_lh_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:44:12 [insn_lh_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:44:12 [insn_lh_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:44:12 [insn_lh_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:44:12 [insn_lh_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:44:13 [insn_lh_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:44:13 [insn_lh_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:44:13 [insn_lh_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:44:13 [insn_lh_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:44:13 [insn_lh_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:44:13 [insn_lh_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:44:14 [insn_lh_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:44:14 [insn_lh_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:44:14 [insn_lh_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:44:14 [insn_lh_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:44:14 [insn_lh_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:44:14 [insn_lh_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:44:16 [insn_lhu_ch0] base: finished (returncode=0) SBY 16:44:16 [insn_lhu_ch0] smt2: starting process "cd insn_lhu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:44:16 [insn_lhu_ch0] smt2: finished (returncode=0) SBY 16:44:16 [insn_lhu_ch0] engine_0: starting process "cd insn_lhu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:44:16 [insn_lhu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:44:17 [insn_lhu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:44:17 [insn_lhu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:44:17 [insn_lhu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:44:17 [insn_lhu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:44:17 [insn_lhu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:44:17 [insn_lhu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:44:18 [insn_lhu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:44:18 [insn_lhu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:44:18 [insn_lhu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:44:18 [insn_lhu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:44:18 [insn_lhu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:44:18 [insn_lhu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:44:18 [insn_lhu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:44:19 [insn_lhu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:44:19 [insn_lhu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:44:19 [insn_lhu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:44:19 [insn_lhu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:44:19 [insn_lhu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:44:19 [insn_lhu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:44:19 [insn_lhu_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:44:20 [insn_lhu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:44:20 [insn_divu_ch0] engine_0: ## 0:00:43 Status: passed SBY 16:44:20 [insn_divu_ch0] engine_0: finished (returncode=0) SBY 16:44:20 [insn_divu_ch0] engine_0: Status returned by engine: pass SBY 16:44:20 [insn_divu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:49 (49) SBY 16:44:20 [insn_divu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:49 (49) SBY 16:44:20 [insn_divu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:44:20 [insn_divu_ch0] DONE (PASS, rc=0) sby insn_lui_ch0.sby SBY 16:44:20 [insn_lui_ch0] Writing 'insn_lui_ch0/src/defines.sv'. SBY 16:44:20 [insn_lui_ch0] Writing 'insn_lui_ch0/src/insn_lui_ch0.sv'. SBY 16:44:20 [insn_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_lui_ch0/src/rvfi_macros.vh'. SBY 16:44:20 [insn_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_lui_ch0/src/rvfi_channel.sv'. SBY 16:44:20 [insn_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_lui_ch0/src/rvfi_testbench.sv'. SBY 16:44:20 [insn_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_lui_ch0/src/rvfi_insn_check.sv'. SBY 16:44:20 [insn_lui_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_lui.v' to 'insn_lui_ch0/src/insn_lui.v'. SBY 16:44:20 [insn_lui_ch0] engine_0: smtbmc --nopresat boolector SBY 16:44:20 [insn_lui_ch0] base: starting process "cd insn_lui_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:44:21 [insn_c_sw_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:44:22 [insn_div_ch0] engine_0: ## 0:00:49 Status: passed SBY 16:44:22 [insn_div_ch0] engine_0: finished (returncode=0) SBY 16:44:22 [insn_div_ch0] engine_0: Status returned by engine: pass SBY 16:44:22 [insn_div_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:55 (55) SBY 16:44:22 [insn_div_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:55 (55) SBY 16:44:22 [insn_div_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:44:22 [insn_div_ch0] DONE (PASS, rc=0) sby insn_lw_ch0.sby SBY 16:44:22 [insn_lw_ch0] Writing 'insn_lw_ch0/src/defines.sv'. SBY 16:44:22 [insn_lw_ch0] Writing 'insn_lw_ch0/src/insn_lw_ch0.sv'. SBY 16:44:22 [insn_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_lw_ch0/src/rvfi_macros.vh'. SBY 16:44:22 [insn_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_lw_ch0/src/rvfi_channel.sv'. SBY 16:44:22 [insn_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_lw_ch0/src/rvfi_testbench.sv'. SBY 16:44:22 [insn_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_lw_ch0/src/rvfi_insn_check.sv'. SBY 16:44:22 [insn_lw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_lw.v' to 'insn_lw_ch0/src/insn_lw.v'. SBY 16:44:22 [insn_lw_ch0] engine_0: smtbmc --nopresat boolector SBY 16:44:22 [insn_lw_ch0] base: starting process "cd insn_lw_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:44:24 [insn_c_swsp_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:44:26 [insn_lui_ch0] base: finished (returncode=0) SBY 16:44:26 [insn_lui_ch0] smt2: starting process "cd insn_lui_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:44:26 [insn_lui_ch0] smt2: finished (returncode=0) SBY 16:44:26 [insn_lui_ch0] engine_0: starting process "cd insn_lui_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:44:26 [insn_lui_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:44:27 [insn_lui_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:44:27 [insn_lui_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:44:27 [insn_lui_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:44:27 [insn_lui_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:44:27 [insn_lui_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:44:27 [insn_lui_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:44:27 [insn_lui_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:44:28 [insn_lui_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:44:28 [insn_lui_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:44:28 [insn_lui_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:44:28 [insn_lui_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:44:28 [insn_lw_ch0] base: finished (returncode=0) SBY 16:44:28 [insn_lw_ch0] smt2: starting process "cd insn_lw_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:44:28 [insn_lui_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:44:28 [insn_lw_ch0] smt2: finished (returncode=0) SBY 16:44:28 [insn_lw_ch0] engine_0: starting process "cd insn_lw_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:44:28 [insn_lui_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:44:28 [insn_lw_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:44:29 [insn_lui_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:44:29 [insn_lw_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:44:29 [insn_lui_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:44:29 [insn_lw_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:44:29 [insn_lui_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:44:29 [insn_lw_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:44:29 [insn_lui_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:44:29 [insn_lw_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:44:29 [insn_lui_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:44:29 [insn_lw_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:44:29 [insn_lui_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:44:29 [insn_lw_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:44:29 [insn_lui_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:44:29 [insn_lw_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:44:30 [insn_lui_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:44:30 [insn_lw_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:44:30 [insn_lw_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:44:30 [insn_lw_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:44:30 [insn_lw_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:44:30 [insn_lw_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:44:30 [insn_lw_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:44:31 [insn_lw_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:44:31 [insn_lw_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:44:31 [insn_lw_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:44:31 [insn_lw_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:44:31 [insn_lw_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:44:31 [insn_lw_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:44:31 [insn_lw_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:44:32 [insn_lw_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:44:32 [insn_c_xor_ch0] engine_0: ## 0:01:03 Status: passed SBY 16:44:32 [insn_c_xor_ch0] engine_0: finished (returncode=0) SBY 16:44:32 [insn_c_xor_ch0] engine_0: Status returned by engine: pass SBY 16:44:32 [insn_c_xor_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:09 (69) SBY 16:44:32 [insn_c_xor_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:09 (69) SBY 16:44:32 [insn_c_xor_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:44:32 [insn_c_xor_ch0] DONE (PASS, rc=0) sby insn_mul_ch0.sby SBY 16:44:32 [insn_mul_ch0] Writing 'insn_mul_ch0/src/defines.sv'. SBY 16:44:32 [insn_mul_ch0] Writing 'insn_mul_ch0/src/insn_mul_ch0.sv'. SBY 16:44:32 [insn_mul_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_mul_ch0/src/rvfi_macros.vh'. SBY 16:44:32 [insn_mul_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_mul_ch0/src/rvfi_channel.sv'. SBY 16:44:32 [insn_mul_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_mul_ch0/src/rvfi_testbench.sv'. SBY 16:44:32 [insn_mul_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_mul_ch0/src/rvfi_insn_check.sv'. SBY 16:44:32 [insn_mul_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_mul.v' to 'insn_mul_ch0/src/insn_mul.v'. SBY 16:44:32 [insn_mul_ch0] engine_0: smtbmc --nopresat boolector SBY 16:44:32 [insn_mul_ch0] base: starting process "cd insn_mul_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:44:37 [insn_mul_ch0] base: finished (returncode=0) SBY 16:44:37 [insn_mul_ch0] smt2: starting process "cd insn_mul_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:44:38 [insn_mul_ch0] smt2: finished (returncode=0) SBY 16:44:38 [insn_mul_ch0] engine_0: starting process "cd insn_mul_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:44:38 [insn_mul_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:44:38 [insn_mul_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:44:38 [insn_mul_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:44:38 [insn_mul_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:44:38 [insn_mul_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:44:38 [insn_mul_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:44:39 [insn_mul_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:44:39 [insn_mul_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:44:39 [insn_mul_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:44:39 [insn_mul_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:44:39 [insn_mul_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:44:39 [insn_mul_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:44:39 [insn_mul_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:44:40 [insn_mul_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:44:40 [insn_mul_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:44:40 [insn_mul_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:44:40 [insn_mul_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:44:40 [insn_mul_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:44:40 [insn_mul_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:44:40 [insn_mul_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:44:41 [insn_mul_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:44:41 [insn_mul_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:44:46 [insn_jal_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:44:49 [insn_jalr_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:44:57 [insn_c_srai_ch0] engine_0: ## 0:02:16 Status: passed SBY 16:44:57 [insn_c_srai_ch0] engine_0: finished (returncode=0) SBY 16:44:57 [insn_c_srai_ch0] engine_0: Status returned by engine: pass SBY 16:44:57 [insn_c_srai_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:44:57 [insn_c_srai_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:44:57 [insn_c_srai_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:44:57 [insn_c_srai_ch0] DONE (PASS, rc=0) sby insn_mulh_ch0.sby SBY 16:44:57 [insn_mulh_ch0] Writing 'insn_mulh_ch0/src/defines.sv'. SBY 16:44:57 [insn_mulh_ch0] Writing 'insn_mulh_ch0/src/insn_mulh_ch0.sv'. SBY 16:44:57 [insn_mulh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_mulh_ch0/src/rvfi_macros.vh'. SBY 16:44:57 [insn_mulh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_mulh_ch0/src/rvfi_channel.sv'. SBY 16:44:57 [insn_mulh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_mulh_ch0/src/rvfi_testbench.sv'. SBY 16:44:57 [insn_mulh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_mulh_ch0/src/rvfi_insn_check.sv'. SBY 16:44:57 [insn_mulh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_mulh.v' to 'insn_mulh_ch0/src/insn_mulh.v'. SBY 16:44:57 [insn_mulh_ch0] engine_0: smtbmc --nopresat boolector SBY 16:44:57 [insn_mulh_ch0] base: starting process "cd insn_mulh_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:44:58 [insn_c_srli_ch0] engine_0: ## 0:02:06 Status: passed SBY 16:44:58 [insn_c_srli_ch0] engine_0: finished (returncode=0) SBY 16:44:58 [insn_c_srli_ch0] engine_0: Status returned by engine: pass SBY 16:44:58 [insn_c_srli_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:11 (131) SBY 16:44:58 [insn_c_srli_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:11 (131) SBY 16:44:58 [insn_c_srli_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:44:58 [insn_c_srli_ch0] DONE (PASS, rc=0) sby insn_mulhsu_ch0.sby SBY 16:44:58 [insn_mulhsu_ch0] Writing 'insn_mulhsu_ch0/src/defines.sv'. SBY 16:44:58 [insn_mulhsu_ch0] Writing 'insn_mulhsu_ch0/src/insn_mulhsu_ch0.sv'. SBY 16:44:58 [insn_mulhsu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_mulhsu_ch0/src/rvfi_macros.vh'. SBY 16:44:58 [insn_mulhsu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_mulhsu_ch0/src/rvfi_channel.sv'. SBY 16:44:58 [insn_mulhsu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_mulhsu_ch0/src/rvfi_testbench.sv'. SBY 16:44:58 [insn_mulhsu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_mulhsu_ch0/src/rvfi_insn_check.sv'. SBY 16:44:58 [insn_mulhsu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_mulhsu.v' to 'insn_mulhsu_ch0/src/insn_mulhsu.v'. SBY 16:44:58 [insn_mulhsu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:44:58 [insn_mulhsu_ch0] base: starting process "cd insn_mulhsu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:45:01 [insn_lb_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:45:03 [insn_mulh_ch0] base: finished (returncode=0) SBY 16:45:03 [insn_mulh_ch0] smt2: starting process "cd insn_mulh_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:03 [insn_mulh_ch0] smt2: finished (returncode=0) SBY 16:45:03 [insn_mulh_ch0] engine_0: starting process "cd insn_mulh_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:03 [insn_mulh_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:45:03 [insn_mulh_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:45:04 [insn_mulh_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:45:04 [insn_mulhsu_ch0] base: finished (returncode=0) SBY 16:45:04 [insn_mulhsu_ch0] smt2: starting process "cd insn_mulhsu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:04 [insn_mulh_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:45:04 [insn_mulh_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:45:04 [insn_mulhsu_ch0] smt2: finished (returncode=0) SBY 16:45:04 [insn_mulhsu_ch0] engine_0: starting process "cd insn_mulhsu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:04 [insn_mulhsu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:45:04 [insn_mulh_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:45:04 [insn_mulhsu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:45:04 [insn_mulh_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:45:04 [insn_mulhsu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:45:04 [insn_mulh_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:45:04 [insn_mulhsu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:45:04 [insn_mulh_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:45:05 [insn_mulhsu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:45:05 [insn_mulh_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:45:05 [insn_mulhsu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:45:05 [insn_mulh_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:45:05 [insn_mulhsu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:45:05 [insn_mulh_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:45:05 [insn_mulh_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:45:05 [insn_mulhsu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:45:05 [insn_mulh_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:45:05 [insn_mulhsu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:45:05 [insn_mulh_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:45:05 [insn_mulhsu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:45:05 [insn_mulh_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:45:05 [insn_mulhsu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:45:06 [insn_mulh_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:45:06 [insn_mulhsu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:45:06 [insn_mulh_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:45:06 [insn_mulhsu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:45:06 [insn_mulh_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:45:06 [insn_mulhsu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:45:06 [insn_mulh_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:45:06 [insn_mulhsu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:45:06 [insn_mulh_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:45:06 [insn_mulhsu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:45:06 [insn_mulh_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:45:06 [insn_mulhsu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:45:06 [insn_mulhsu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:45:07 [insn_mulhsu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:45:07 [insn_mulhsu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:45:07 [insn_mulhsu_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:45:07 [insn_mulhsu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:45:09 [insn_lbu_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:45:14 [insn_c_slli_ch0] engine_0: ## 0:02:52 Status: passed SBY 16:45:14 [insn_c_slli_ch0] engine_0: finished (returncode=0) SBY 16:45:14 [insn_c_slli_ch0] engine_0: Status returned by engine: pass SBY 16:45:14 [insn_c_slli_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:58 (178) SBY 16:45:14 [insn_c_slli_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:58 (178) SBY 16:45:14 [insn_c_slli_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:45:14 [insn_c_slli_ch0] DONE (PASS, rc=0) sby insn_mulhu_ch0.sby SBY 16:45:15 [insn_lh_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:45:15 [insn_mulhu_ch0] Writing 'insn_mulhu_ch0/src/defines.sv'. SBY 16:45:15 [insn_mulhu_ch0] Writing 'insn_mulhu_ch0/src/insn_mulhu_ch0.sv'. SBY 16:45:15 [insn_mulhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_mulhu_ch0/src/rvfi_macros.vh'. SBY 16:45:15 [insn_mulhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_mulhu_ch0/src/rvfi_channel.sv'. SBY 16:45:15 [insn_mulhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_mulhu_ch0/src/rvfi_testbench.sv'. SBY 16:45:15 [insn_mulhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_mulhu_ch0/src/rvfi_insn_check.sv'. SBY 16:45:15 [insn_mulhu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_mulhu.v' to 'insn_mulhu_ch0/src/insn_mulhu.v'. SBY 16:45:15 [insn_mulhu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:45:15 [insn_mulhu_ch0] base: starting process "cd insn_mulhu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:45:20 [insn_c_sub_ch0] engine_0: ## 0:02:27 Status: passed SBY 16:45:20 [insn_lhu_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:45:20 [insn_c_sub_ch0] engine_0: finished (returncode=0) SBY 16:45:20 [insn_c_sub_ch0] engine_0: Status returned by engine: pass SBY 16:45:20 [insn_c_sub_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:33 (153) SBY 16:45:20 [insn_c_sub_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:33 (153) SBY 16:45:20 [insn_c_sub_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:45:20 [insn_c_sub_ch0] DONE (PASS, rc=0) sby insn_or_ch0.sby SBY 16:45:20 [insn_or_ch0] Writing 'insn_or_ch0/src/defines.sv'. SBY 16:45:20 [insn_or_ch0] Writing 'insn_or_ch0/src/insn_or_ch0.sv'. SBY 16:45:20 [insn_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_or_ch0/src/rvfi_macros.vh'. SBY 16:45:20 [insn_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_or_ch0/src/rvfi_channel.sv'. SBY 16:45:20 [insn_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_or_ch0/src/rvfi_testbench.sv'. SBY 16:45:20 [insn_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_or_ch0/src/rvfi_insn_check.sv'. SBY 16:45:20 [insn_or_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_or.v' to 'insn_or_ch0/src/insn_or.v'. SBY 16:45:20 [insn_or_ch0] engine_0: smtbmc --nopresat boolector SBY 16:45:20 [insn_or_ch0] base: starting process "cd insn_or_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:45:20 [insn_mulhu_ch0] base: finished (returncode=0) SBY 16:45:20 [insn_mulhu_ch0] smt2: starting process "cd insn_mulhu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:20 [insn_mulhu_ch0] smt2: finished (returncode=0) SBY 16:45:20 [insn_mulhu_ch0] engine_0: starting process "cd insn_mulhu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:20 [insn_mulhu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:45:21 [insn_mulhu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:45:21 [insn_mulhu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:45:21 [insn_mulhu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:45:21 [insn_mulhu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:45:21 [insn_mulhu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:45:21 [insn_mulhu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:45:22 [insn_mulhu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:45:22 [insn_mulhu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:45:22 [insn_mulhu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:45:22 [insn_mulhu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:45:22 [insn_mulhu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:45:22 [insn_mulhu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:45:22 [insn_mulhu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:45:23 [insn_mulhu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:45:23 [insn_mulhu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:45:23 [insn_mulhu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:45:23 [insn_mulhu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:45:23 [insn_mulhu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:45:23 [insn_mulhu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:45:23 [insn_mulhu_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:45:24 [insn_mulhu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:45:25 [insn_or_ch0] base: finished (returncode=0) SBY 16:45:25 [insn_or_ch0] smt2: starting process "cd insn_or_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:26 [insn_or_ch0] smt2: finished (returncode=0) SBY 16:45:26 [insn_or_ch0] engine_0: starting process "cd insn_or_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:26 [insn_or_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:45:26 [insn_or_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:45:26 [insn_or_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:45:26 [insn_or_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:45:26 [insn_or_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:45:26 [insn_or_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:45:27 [insn_or_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:45:27 [insn_or_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:45:27 [insn_or_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:45:27 [insn_or_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:45:27 [insn_or_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:45:27 [insn_or_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:45:27 [insn_or_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:45:28 [insn_or_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:45:28 [insn_or_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:45:28 [insn_or_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:45:28 [insn_or_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:45:28 [insn_or_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:45:28 [insn_or_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:45:29 [insn_or_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:45:29 [insn_or_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:45:29 [insn_or_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:45:30 [insn_lui_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:45:32 [insn_lw_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:45:34 [insn_lui_ch0] engine_0: ## 0:01:07 Status: passed SBY 16:45:34 [insn_lui_ch0] engine_0: finished (returncode=0) SBY 16:45:34 [insn_lui_ch0] engine_0: Status returned by engine: pass SBY 16:45:34 [insn_lui_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:13 (73) SBY 16:45:34 [insn_lui_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:13 (73) SBY 16:45:34 [insn_lui_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:45:34 [insn_lui_ch0] DONE (PASS, rc=0) sby insn_ori_ch0.sby SBY 16:45:34 [insn_ori_ch0] Writing 'insn_ori_ch0/src/defines.sv'. SBY 16:45:34 [insn_ori_ch0] Writing 'insn_ori_ch0/src/insn_ori_ch0.sv'. SBY 16:45:34 [insn_ori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_ori_ch0/src/rvfi_macros.vh'. SBY 16:45:34 [insn_ori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_ori_ch0/src/rvfi_channel.sv'. SBY 16:45:34 [insn_ori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_ori_ch0/src/rvfi_testbench.sv'. SBY 16:45:34 [insn_ori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_ori_ch0/src/rvfi_insn_check.sv'. SBY 16:45:34 [insn_ori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_ori.v' to 'insn_ori_ch0/src/insn_ori.v'. SBY 16:45:34 [insn_ori_ch0] engine_0: smtbmc --nopresat boolector SBY 16:45:34 [insn_ori_ch0] base: starting process "cd insn_ori_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:45:37 [insn_jalr_ch0] engine_0: ## 0:01:51 Status: passed SBY 16:45:37 [insn_jalr_ch0] engine_0: finished (returncode=0) SBY 16:45:37 [insn_jalr_ch0] engine_0: Status returned by engine: pass SBY 16:45:37 [insn_jalr_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:57 (117) SBY 16:45:37 [insn_jalr_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:57 (117) SBY 16:45:37 [insn_jalr_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:45:37 [insn_jalr_ch0] DONE (PASS, rc=0) sby insn_rem_ch0.sby SBY 16:45:37 [insn_rem_ch0] Writing 'insn_rem_ch0/src/defines.sv'. SBY 16:45:37 [insn_rem_ch0] Writing 'insn_rem_ch0/src/insn_rem_ch0.sv'. SBY 16:45:37 [insn_rem_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_rem_ch0/src/rvfi_macros.vh'. SBY 16:45:37 [insn_rem_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_rem_ch0/src/rvfi_channel.sv'. SBY 16:45:37 [insn_rem_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_rem_ch0/src/rvfi_testbench.sv'. SBY 16:45:37 [insn_rem_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_rem_ch0/src/rvfi_insn_check.sv'. SBY 16:45:37 [insn_rem_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_rem.v' to 'insn_rem_ch0/src/insn_rem.v'. SBY 16:45:37 [insn_rem_ch0] engine_0: smtbmc --nopresat boolector SBY 16:45:37 [insn_rem_ch0] base: starting process "cd insn_rem_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:45:40 [insn_ori_ch0] base: finished (returncode=0) SBY 16:45:40 [insn_ori_ch0] smt2: starting process "cd insn_ori_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:40 [insn_ori_ch0] smt2: finished (returncode=0) SBY 16:45:40 [insn_ori_ch0] engine_0: starting process "cd insn_ori_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:40 [insn_ori_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:45:40 [insn_ori_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:45:41 [insn_ori_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:45:41 [insn_ori_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:45:41 [insn_ori_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:45:41 [insn_mul_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:45:41 [insn_ori_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:45:41 [insn_ori_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:45:41 [insn_ori_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:45:41 [insn_ori_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:45:42 [insn_ori_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:45:42 [insn_ori_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:45:42 [insn_ori_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:45:42 [insn_ori_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:45:42 [insn_ori_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:45:42 [insn_ori_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:45:42 [insn_ori_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:45:43 [insn_rem_ch0] base: finished (returncode=0) SBY 16:45:43 [insn_rem_ch0] smt2: starting process "cd insn_rem_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:43 [insn_ori_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:45:43 [insn_rem_ch0] smt2: finished (returncode=0) SBY 16:45:43 [insn_rem_ch0] engine_0: starting process "cd insn_rem_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:43 [insn_ori_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:45:43 [insn_rem_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:45:43 [insn_ori_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:45:43 [insn_rem_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:45:43 [insn_ori_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:45:43 [insn_rem_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:45:43 [insn_ori_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:45:43 [insn_rem_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:45:43 [insn_ori_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:45:43 [insn_rem_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:45:43 [insn_rem_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:45:44 [insn_rem_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:45:44 [insn_rem_ch0] engine_0: ## 0:00:00 Skipping step 6.. SBY 16:45:44 [insn_rem_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:45:44 [insn_rem_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:45:44 [insn_rem_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:45:44 [insn_rem_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:45:44 [insn_rem_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:45:45 [insn_rem_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:45:45 [insn_rem_ch0] engine_0: ## 0:00:01 Skipping step 13.. SBY 16:45:45 [insn_rem_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:45:45 [insn_rem_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:45:45 [insn_rem_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:45:45 [insn_rem_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:45:45 [insn_rem_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:45:46 [insn_rem_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:45:46 [insn_rem_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:45:49 [insn_c_swsp_ch0] engine_0: ## 0:02:27 Status: passed SBY 16:45:49 [insn_c_swsp_ch0] engine_0: finished (returncode=0) SBY 16:45:49 [insn_c_swsp_ch0] engine_0: Status returned by engine: pass SBY 16:45:49 [insn_c_swsp_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:33 (153) SBY 16:45:49 [insn_c_swsp_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:33 (153) SBY 16:45:49 [insn_c_swsp_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:45:49 [insn_c_swsp_ch0] DONE (PASS, rc=0) sby insn_remu_ch0.sby SBY 16:45:49 [insn_remu_ch0] Writing 'insn_remu_ch0/src/defines.sv'. SBY 16:45:49 [insn_remu_ch0] Writing 'insn_remu_ch0/src/insn_remu_ch0.sv'. SBY 16:45:49 [insn_remu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_remu_ch0/src/rvfi_macros.vh'. SBY 16:45:49 [insn_remu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_remu_ch0/src/rvfi_channel.sv'. SBY 16:45:49 [insn_remu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_remu_ch0/src/rvfi_testbench.sv'. SBY 16:45:49 [insn_remu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_remu_ch0/src/rvfi_insn_check.sv'. SBY 16:45:49 [insn_remu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_remu.v' to 'insn_remu_ch0/src/insn_remu.v'. SBY 16:45:49 [insn_remu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:45:49 [insn_remu_ch0] base: starting process "cd insn_remu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:45:52 [insn_c_sw_ch0] engine_0: ## 0:02:34 Status: passed SBY 16:45:52 [insn_c_sw_ch0] engine_0: finished (returncode=0) SBY 16:45:52 [insn_c_sw_ch0] engine_0: Status returned by engine: pass SBY 16:45:52 [insn_c_sw_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:40 (160) SBY 16:45:52 [insn_c_sw_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:40 (160) SBY 16:45:52 [insn_c_sw_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:45:52 [insn_c_sw_ch0] DONE (PASS, rc=0) sby insn_sb_ch0.sby SBY 16:45:52 [insn_sb_ch0] Writing 'insn_sb_ch0/src/defines.sv'. SBY 16:45:52 [insn_sb_ch0] Writing 'insn_sb_ch0/src/insn_sb_ch0.sv'. SBY 16:45:52 [insn_sb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_sb_ch0/src/rvfi_macros.vh'. SBY 16:45:52 [insn_sb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_sb_ch0/src/rvfi_channel.sv'. SBY 16:45:52 [insn_sb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_sb_ch0/src/rvfi_testbench.sv'. SBY 16:45:52 [insn_sb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_sb_ch0/src/rvfi_insn_check.sv'. SBY 16:45:52 [insn_sb_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_sb.v' to 'insn_sb_ch0/src/insn_sb.v'. SBY 16:45:52 [insn_sb_ch0] engine_0: smtbmc --nopresat boolector SBY 16:45:52 [insn_sb_ch0] base: starting process "cd insn_sb_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:45:54 [insn_jal_ch0] engine_0: ## 0:02:11 Status: passed SBY 16:45:54 [insn_jal_ch0] engine_0: finished (returncode=0) SBY 16:45:54 [insn_jal_ch0] engine_0: Status returned by engine: pass SBY 16:45:54 [insn_jal_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:16 (136) SBY 16:45:54 [insn_jal_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:16 (136) SBY 16:45:54 [insn_jal_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:45:54 [insn_jal_ch0] DONE (PASS, rc=0) sby insn_sh_ch0.sby SBY 16:45:54 [insn_sh_ch0] Writing 'insn_sh_ch0/src/defines.sv'. SBY 16:45:54 [insn_sh_ch0] Writing 'insn_sh_ch0/src/insn_sh_ch0.sv'. SBY 16:45:54 [insn_sh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_sh_ch0/src/rvfi_macros.vh'. SBY 16:45:54 [insn_sh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_sh_ch0/src/rvfi_channel.sv'. SBY 16:45:54 [insn_sh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_sh_ch0/src/rvfi_testbench.sv'. SBY 16:45:54 [insn_sh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_sh_ch0/src/rvfi_insn_check.sv'. SBY 16:45:54 [insn_sh_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_sh.v' to 'insn_sh_ch0/src/insn_sh.v'. SBY 16:45:54 [insn_sh_ch0] engine_0: smtbmc --nopresat boolector SBY 16:45:54 [insn_sh_ch0] base: starting process "cd insn_sh_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:45:54 [insn_remu_ch0] base: finished (returncode=0) SBY 16:45:54 [insn_remu_ch0] smt2: starting process "cd insn_remu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:54 [insn_remu_ch0] smt2: finished (returncode=0) SBY 16:45:54 [insn_remu_ch0] engine_0: starting process "cd insn_remu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:54 [insn_remu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:45:54 [insn_remu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:45:55 [insn_remu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:45:55 [insn_remu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:45:55 [insn_remu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:45:55 [insn_remu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:45:55 [insn_remu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:45:55 [insn_remu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:45:55 [insn_remu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:45:56 [insn_remu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:45:56 [insn_remu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:45:56 [insn_remu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:45:56 [insn_remu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:45:56 [insn_remu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:45:56 [insn_remu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:45:56 [insn_remu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:45:57 [insn_remu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:45:57 [insn_remu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:45:57 [insn_remu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:45:57 [insn_remu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:45:57 [insn_remu_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:45:57 [insn_sb_ch0] base: finished (returncode=0) SBY 16:45:57 [insn_sb_ch0] smt2: starting process "cd insn_sb_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:57 [insn_remu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:45:57 [insn_sb_ch0] smt2: finished (returncode=0) SBY 16:45:57 [insn_sb_ch0] engine_0: starting process "cd insn_sb_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:58 [insn_sb_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:45:58 [insn_sb_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:45:58 [insn_sb_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:45:58 [insn_sb_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:45:58 [insn_sb_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:45:58 [insn_sb_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:45:58 [insn_sb_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:45:59 [insn_sb_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:45:59 [insn_sb_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:45:59 [insn_sb_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:45:59 [insn_sb_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:45:59 [insn_sb_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:45:59 [insn_sh_ch0] base: finished (returncode=0) SBY 16:45:59 [insn_sh_ch0] smt2: starting process "cd insn_sh_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:45:59 [insn_sb_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:45:59 [insn_sh_ch0] smt2: finished (returncode=0) SBY 16:45:59 [insn_sh_ch0] engine_0: starting process "cd insn_sh_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:45:59 [insn_sb_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:46:00 [insn_sh_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:46:00 [insn_sb_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:46:00 [insn_sh_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:46:00 [insn_sb_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:46:00 [insn_sh_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:46:00 [insn_sb_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:46:00 [insn_sh_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:46:00 [insn_sb_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:46:00 [insn_sh_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:46:00 [insn_sb_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:46:00 [insn_sh_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:46:00 [insn_sh_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:46:00 [insn_sb_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:46:01 [insn_sh_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:46:01 [insn_sb_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:46:01 [insn_sh_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:46:01 [insn_sb_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:46:01 [insn_sh_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:46:01 [insn_sh_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:46:01 [insn_sh_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:46:01 [insn_sh_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:46:01 [insn_sh_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:46:02 [insn_sh_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:46:02 [insn_sh_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:46:02 [insn_sh_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:46:02 [insn_sh_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:46:02 [insn_sh_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:46:02 [insn_sh_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:46:02 [insn_sh_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:46:03 [insn_sh_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:46:06 [insn_mulh_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:46:07 [insn_mulhsu_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:46:11 [insn_mul_ch0] engine_0: ## 0:01:33 Status: passed SBY 16:46:11 [insn_mul_ch0] engine_0: finished (returncode=0) SBY 16:46:11 [insn_mul_ch0] engine_0: Status returned by engine: pass SBY 16:46:11 [insn_mul_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:39 (99) SBY 16:46:11 [insn_mul_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:38 (98) SBY 16:46:11 [insn_mul_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:11 [insn_mul_ch0] DONE (PASS, rc=0) sby insn_sll_ch0.sby SBY 16:46:11 [insn_sll_ch0] Writing 'insn_sll_ch0/src/defines.sv'. SBY 16:46:11 [insn_sll_ch0] Writing 'insn_sll_ch0/src/insn_sll_ch0.sv'. SBY 16:46:11 [insn_sll_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_sll_ch0/src/rvfi_macros.vh'. SBY 16:46:11 [insn_sll_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_sll_ch0/src/rvfi_channel.sv'. SBY 16:46:11 [insn_sll_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_sll_ch0/src/rvfi_testbench.sv'. SBY 16:46:11 [insn_sll_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_sll_ch0/src/rvfi_insn_check.sv'. SBY 16:46:11 [insn_sll_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_sll.v' to 'insn_sll_ch0/src/insn_sll.v'. SBY 16:46:11 [insn_sll_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:11 [insn_sll_ch0] base: starting process "cd insn_sll_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:17 [insn_sll_ch0] base: finished (returncode=0) SBY 16:46:17 [insn_sll_ch0] smt2: starting process "cd insn_sll_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:46:17 [insn_sll_ch0] smt2: finished (returncode=0) SBY 16:46:17 [insn_sll_ch0] engine_0: starting process "cd insn_sll_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:46:17 [insn_sll_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:46:17 [insn_sll_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:46:17 [insn_sll_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:46:17 [insn_sll_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:46:18 [insn_sll_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:46:18 [insn_sll_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:46:18 [insn_sll_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:46:18 [insn_sll_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:46:18 [insn_sll_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:46:18 [insn_sll_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:46:18 [insn_sll_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:46:19 [insn_sll_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:46:19 [insn_sll_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:46:19 [insn_sll_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:46:19 [insn_sll_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:46:19 [insn_sll_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:46:19 [insn_sll_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:46:20 [insn_sll_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:46:20 [insn_sll_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:46:20 [insn_sll_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:46:20 [insn_sll_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:46:20 [insn_sll_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:46:24 [insn_mulhu_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:46:24 [insn_rem_ch0] engine_0: ## 0:00:41 Status: passed SBY 16:46:24 [insn_rem_ch0] engine_0: finished (returncode=0) SBY 16:46:24 [insn_rem_ch0] engine_0: Status returned by engine: pass SBY 16:46:24 [insn_rem_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:46 (46) SBY 16:46:24 [insn_rem_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:46 (46) SBY 16:46:24 [insn_rem_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:24 [insn_rem_ch0] DONE (PASS, rc=0) sby insn_slli_ch0.sby SBY 16:46:24 [insn_slli_ch0] Writing 'insn_slli_ch0/src/defines.sv'. SBY 16:46:24 [insn_slli_ch0] Writing 'insn_slli_ch0/src/insn_slli_ch0.sv'. SBY 16:46:24 [insn_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_slli_ch0/src/rvfi_macros.vh'. SBY 16:46:24 [insn_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_slli_ch0/src/rvfi_channel.sv'. SBY 16:46:24 [insn_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_slli_ch0/src/rvfi_testbench.sv'. SBY 16:46:24 [insn_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_slli_ch0/src/rvfi_insn_check.sv'. SBY 16:46:24 [insn_slli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_slli.v' to 'insn_slli_ch0/src/insn_slli.v'. SBY 16:46:24 [insn_slli_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:24 [insn_slli_ch0] base: starting process "cd insn_slli_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:29 [insn_or_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:46:30 [insn_slli_ch0] base: finished (returncode=0) SBY 16:46:30 [insn_slli_ch0] smt2: starting process "cd insn_slli_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:46:30 [insn_slli_ch0] smt2: finished (returncode=0) SBY 16:46:30 [insn_slli_ch0] engine_0: starting process "cd insn_slli_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:46:30 [insn_slli_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:46:30 [insn_slli_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:46:30 [insn_slli_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:46:30 [insn_slli_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:46:31 [insn_slli_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:46:31 [insn_slli_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:46:31 [insn_slli_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:46:31 [insn_slli_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:46:31 [insn_slli_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:46:31 [insn_lh_ch0] engine_0: ## 0:02:20 Status: passed SBY 16:46:31 [insn_lh_ch0] engine_0: finished (returncode=0) SBY 16:46:31 [insn_lh_ch0] engine_0: Status returned by engine: pass SBY 16:46:31 [insn_lh_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:26 (146) SBY 16:46:31 [insn_lh_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:26 (146) SBY 16:46:31 [insn_lh_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:31 [insn_lh_ch0] DONE (PASS, rc=0) SBY 16:46:31 [insn_slli_ch0] engine_0: ## 0:00:01 Skipping step 8.. sby insn_slt_ch0.sby SBY 16:46:31 [insn_slt_ch0] Writing 'insn_slt_ch0/src/defines.sv'. SBY 16:46:31 [insn_slt_ch0] Writing 'insn_slt_ch0/src/insn_slt_ch0.sv'. SBY 16:46:31 [insn_slt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_slt_ch0/src/rvfi_macros.vh'. SBY 16:46:31 [insn_slt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_slt_ch0/src/rvfi_channel.sv'. SBY 16:46:31 [insn_slt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_slt_ch0/src/rvfi_testbench.sv'. SBY 16:46:31 [insn_slt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_slt_ch0/src/rvfi_insn_check.sv'. SBY 16:46:31 [insn_slt_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_slt.v' to 'insn_slt_ch0/src/insn_slt.v'. SBY 16:46:31 [insn_slt_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:31 [insn_slt_ch0] base: starting process "cd insn_slt_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:31 [insn_slli_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:46:32 [insn_slli_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:46:32 [insn_slli_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:46:32 [insn_slli_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:46:32 [insn_slli_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:46:32 [insn_slli_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:46:32 [insn_slli_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:46:33 [insn_slli_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:46:33 [insn_slli_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:46:33 [insn_slli_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:46:33 [insn_slli_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:46:33 [insn_slli_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:46:33 [insn_remu_ch0] engine_0: ## 0:00:39 Status: passed SBY 16:46:33 [insn_remu_ch0] engine_0: finished (returncode=0) SBY 16:46:33 [insn_remu_ch0] engine_0: Status returned by engine: pass SBY 16:46:33 [insn_remu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:44 (44) SBY 16:46:33 [insn_remu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:44 (44) SBY 16:46:33 [insn_remu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:33 [insn_remu_ch0] DONE (PASS, rc=0) sby insn_slti_ch0.sby SBY 16:46:33 [insn_slti_ch0] Writing 'insn_slti_ch0/src/defines.sv'. SBY 16:46:33 [insn_slti_ch0] Writing 'insn_slti_ch0/src/insn_slti_ch0.sv'. SBY 16:46:33 [insn_slti_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_slti_ch0/src/rvfi_macros.vh'. SBY 16:46:33 [insn_slti_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_slti_ch0/src/rvfi_channel.sv'. SBY 16:46:33 [insn_slti_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_slti_ch0/src/rvfi_testbench.sv'. SBY 16:46:33 [insn_slti_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_slti_ch0/src/rvfi_insn_check.sv'. SBY 16:46:33 [insn_slti_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_slti.v' to 'insn_slti_ch0/src/insn_slti.v'. SBY 16:46:33 [insn_slti_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:33 [insn_slti_ch0] base: starting process "cd insn_slti_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:37 [insn_slt_ch0] base: finished (returncode=0) SBY 16:46:37 [insn_slt_ch0] smt2: starting process "cd insn_slt_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:46:37 [insn_slt_ch0] smt2: finished (returncode=0) SBY 16:46:37 [insn_slt_ch0] engine_0: starting process "cd insn_slt_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:46:37 [insn_slt_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:46:37 [insn_slt_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:46:37 [insn_slt_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:46:37 [insn_slt_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:46:37 [insn_slt_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:46:38 [insn_slt_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:46:38 [insn_slt_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:46:38 [insn_slt_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:46:38 [insn_slt_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:46:38 [insn_slt_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:46:38 [insn_slt_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:46:39 [insn_slt_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:46:39 [insn_slt_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:46:39 [insn_slt_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:46:39 [insn_slt_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:46:39 [insn_slti_ch0] base: finished (returncode=0) SBY 16:46:39 [insn_slti_ch0] smt2: starting process "cd insn_slti_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:46:39 [insn_slt_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:46:39 [insn_slti_ch0] smt2: finished (returncode=0) SBY 16:46:39 [insn_slti_ch0] engine_0: starting process "cd insn_slti_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:46:39 [insn_slt_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:46:39 [insn_slti_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:46:39 [insn_slt_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:46:39 [insn_slti_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:46:40 [insn_slt_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:46:40 [insn_slti_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:46:40 [insn_slt_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:46:40 [insn_slti_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:46:40 [insn_slt_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:46:40 [insn_slti_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:46:40 [insn_slt_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:46:40 [insn_slti_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:46:40 [insn_slti_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:46:40 [insn_slti_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:46:40 [insn_slti_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:46:41 [insn_slti_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:46:41 [insn_slti_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:46:41 [insn_slti_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:46:41 [insn_slti_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:46:41 [insn_slti_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:46:41 [insn_slti_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:46:42 [insn_slti_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:46:42 [insn_slti_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:46:42 [insn_slti_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:46:42 [insn_slti_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:46:42 [insn_slti_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:46:42 [insn_slti_ch0] engine_0: ## 0:00:03 Skipping step 19.. SBY 16:46:42 [insn_slti_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:46:44 [insn_ori_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:46:45 [insn_mulhsu_ch0] engine_0: ## 0:01:41 Status: passed SBY 16:46:45 [insn_mulhsu_ch0] engine_0: finished (returncode=0) SBY 16:46:45 [insn_mulhsu_ch0] engine_0: Status returned by engine: pass SBY 16:46:45 [insn_mulhsu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:47 (107) SBY 16:46:45 [insn_mulhsu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:47 (107) SBY 16:46:45 [insn_mulhsu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:45 [insn_mulhsu_ch0] DONE (PASS, rc=0) sby insn_sltiu_ch0.sby SBY 16:46:46 [insn_sltiu_ch0] Writing 'insn_sltiu_ch0/src/defines.sv'. SBY 16:46:46 [insn_sltiu_ch0] Writing 'insn_sltiu_ch0/src/insn_sltiu_ch0.sv'. SBY 16:46:46 [insn_sltiu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_sltiu_ch0/src/rvfi_macros.vh'. SBY 16:46:46 [insn_sltiu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_sltiu_ch0/src/rvfi_channel.sv'. SBY 16:46:46 [insn_sltiu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_sltiu_ch0/src/rvfi_testbench.sv'. SBY 16:46:46 [insn_sltiu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_sltiu_ch0/src/rvfi_insn_check.sv'. SBY 16:46:46 [insn_sltiu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_sltiu.v' to 'insn_sltiu_ch0/src/insn_sltiu.v'. SBY 16:46:46 [insn_sltiu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:46 [insn_sltiu_ch0] base: starting process "cd insn_sltiu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:51 [insn_sltiu_ch0] base: finished (returncode=0) SBY 16:46:51 [insn_sltiu_ch0] smt2: starting process "cd insn_sltiu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:46:51 [insn_mulhu_ch0] engine_0: ## 0:01:30 Status: passed SBY 16:46:51 [insn_mulhu_ch0] engine_0: finished (returncode=0) SBY 16:46:51 [insn_mulhu_ch0] engine_0: Status returned by engine: pass SBY 16:46:51 [insn_mulhu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:36 (96) SBY 16:46:51 [insn_mulhu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:36 (96) SBY 16:46:51 [insn_mulhu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:51 [insn_mulhu_ch0] DONE (PASS, rc=0) sby insn_sltu_ch0.sby SBY 16:46:51 [insn_sltiu_ch0] smt2: finished (returncode=0) SBY 16:46:51 [insn_sltiu_ch0] engine_0: starting process "cd insn_sltiu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:46:51 [insn_sltu_ch0] Writing 'insn_sltu_ch0/src/defines.sv'. SBY 16:46:51 [insn_sltu_ch0] Writing 'insn_sltu_ch0/src/insn_sltu_ch0.sv'. SBY 16:46:51 [insn_sltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_sltu_ch0/src/rvfi_macros.vh'. SBY 16:46:51 [insn_sltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_sltu_ch0/src/rvfi_channel.sv'. SBY 16:46:51 [insn_sltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_sltu_ch0/src/rvfi_testbench.sv'. SBY 16:46:51 [insn_sltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_sltu_ch0/src/rvfi_insn_check.sv'. SBY 16:46:51 [insn_sltu_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_sltu.v' to 'insn_sltu_ch0/src/insn_sltu.v'. SBY 16:46:51 [insn_sltu_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:51 [insn_sltu_ch0] base: starting process "cd insn_sltu_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:51 [insn_sltiu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:46:52 [insn_sltiu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:46:52 [insn_sltiu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:46:52 [insn_sltiu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:46:52 [insn_sltiu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:46:52 [insn_ori_ch0] engine_0: ## 0:01:11 Status: passed SBY 16:46:52 [insn_ori_ch0] engine_0: finished (returncode=0) SBY 16:46:52 [insn_ori_ch0] engine_0: Status returned by engine: pass SBY 16:46:52 [insn_ori_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:17 (77) SBY 16:46:52 [insn_ori_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:17 (77) SBY 16:46:52 [insn_ori_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:52 [insn_ori_ch0] DONE (PASS, rc=0) sby insn_sra_ch0.sby SBY 16:46:52 [insn_sra_ch0] Writing 'insn_sra_ch0/src/defines.sv'. SBY 16:46:52 [insn_sra_ch0] Writing 'insn_sra_ch0/src/insn_sra_ch0.sv'. SBY 16:46:52 [insn_sra_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_sra_ch0/src/rvfi_macros.vh'. SBY 16:46:52 [insn_sra_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_sra_ch0/src/rvfi_channel.sv'. SBY 16:46:52 [insn_sra_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_sra_ch0/src/rvfi_testbench.sv'. SBY 16:46:52 [insn_sra_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_sra_ch0/src/rvfi_insn_check.sv'. SBY 16:46:52 [insn_sra_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_sra.v' to 'insn_sra_ch0/src/insn_sra.v'. SBY 16:46:52 [insn_sra_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:52 [insn_sra_ch0] base: starting process "cd insn_sra_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:52 [insn_sltiu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:46:52 [insn_sltiu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:46:52 [insn_sltiu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:46:53 [insn_sltiu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:46:53 [insn_sltiu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:46:53 [insn_sltiu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:46:53 [insn_sltiu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:46:53 [insn_sltiu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:46:53 [insn_sltiu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:46:53 [insn_sltiu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:46:54 [insn_sltiu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:46:54 [insn_sltiu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:46:54 [insn_sltiu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:46:54 [insn_sltiu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:46:54 [insn_sltiu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:46:54 [insn_mulh_ch0] engine_0: ## 0:01:50 Status: passed SBY 16:46:54 [insn_mulh_ch0] engine_0: finished (returncode=0) SBY 16:46:54 [insn_mulh_ch0] engine_0: Status returned by engine: pass SBY 16:46:54 [insn_mulh_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:56 (116) SBY 16:46:54 [insn_mulh_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:56 (116) SBY 16:46:54 [insn_mulh_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:54 [insn_mulh_ch0] DONE (PASS, rc=0) sby insn_srai_ch0.sby SBY 16:46:54 [insn_sltiu_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:46:54 [insn_srai_ch0] Writing 'insn_srai_ch0/src/defines.sv'. SBY 16:46:54 [insn_srai_ch0] Writing 'insn_srai_ch0/src/insn_srai_ch0.sv'. SBY 16:46:54 [insn_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_srai_ch0/src/rvfi_macros.vh'. SBY 16:46:54 [insn_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_srai_ch0/src/rvfi_channel.sv'. SBY 16:46:54 [insn_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_srai_ch0/src/rvfi_testbench.sv'. SBY 16:46:54 [insn_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_srai_ch0/src/rvfi_insn_check.sv'. SBY 16:46:54 [insn_srai_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_srai.v' to 'insn_srai_ch0/src/insn_srai.v'. SBY 16:46:54 [insn_srai_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:54 [insn_srai_ch0] base: starting process "cd insn_srai_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:54 [insn_sltiu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:46:54 [insn_lhu_ch0] engine_0: ## 0:02:38 Status: passed SBY 16:46:55 [insn_lhu_ch0] engine_0: finished (returncode=0) SBY 16:46:55 [insn_lhu_ch0] engine_0: Status returned by engine: pass SBY 16:46:55 [insn_lhu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:44 (164) SBY 16:46:55 [insn_lhu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:44 (164) SBY 16:46:55 [insn_lhu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:46:55 [insn_lhu_ch0] DONE (PASS, rc=0) sby insn_srl_ch0.sby SBY 16:46:55 [insn_srl_ch0] Writing 'insn_srl_ch0/src/defines.sv'. SBY 16:46:55 [insn_srl_ch0] Writing 'insn_srl_ch0/src/insn_srl_ch0.sv'. SBY 16:46:55 [insn_srl_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_srl_ch0/src/rvfi_macros.vh'. SBY 16:46:55 [insn_srl_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_srl_ch0/src/rvfi_channel.sv'. SBY 16:46:55 [insn_srl_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_srl_ch0/src/rvfi_testbench.sv'. SBY 16:46:55 [insn_srl_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_srl_ch0/src/rvfi_insn_check.sv'. SBY 16:46:55 [insn_srl_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_srl.v' to 'insn_srl_ch0/src/insn_srl.v'. SBY 16:46:55 [insn_srl_ch0] engine_0: smtbmc --nopresat boolector SBY 16:46:55 [insn_srl_ch0] base: starting process "cd insn_srl_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:46:57 [insn_sltu_ch0] base: finished (returncode=0) SBY 16:46:57 [insn_sltu_ch0] smt2: starting process "cd insn_sltu_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:46:57 [insn_sltu_ch0] smt2: finished (returncode=0) SBY 16:46:57 [insn_sltu_ch0] engine_0: starting process "cd insn_sltu_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:46:57 [insn_sltu_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:46:57 [insn_sltu_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:46:57 [insn_sltu_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:46:57 [insn_sltu_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:46:57 [insn_sra_ch0] base: finished (returncode=0) SBY 16:46:57 [insn_sra_ch0] smt2: starting process "cd insn_sra_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:46:58 [insn_sltu_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:46:58 [insn_sra_ch0] smt2: finished (returncode=0) SBY 16:46:58 [insn_sra_ch0] engine_0: starting process "cd insn_sra_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:46:58 [insn_sltu_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:46:58 [insn_sra_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:46:58 [insn_sltu_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:46:58 [insn_sra_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:46:58 [insn_sltu_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:46:58 [insn_sra_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:46:58 [insn_sltu_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:46:58 [insn_sra_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:46:58 [insn_sltu_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:46:58 [insn_sra_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:46:58 [insn_sltu_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:46:58 [insn_sra_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:46:59 [insn_sltu_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:46:59 [insn_sra_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:46:59 [insn_sltu_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:46:59 [insn_sra_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:46:59 [insn_sltu_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:46:59 [insn_sra_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:46:59 [insn_sltu_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:46:59 [insn_sra_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:46:59 [insn_sltu_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:46:59 [insn_sra_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:46:59 [insn_sltu_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:46:59 [insn_sra_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:46:59 [insn_sltu_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:46:59 [insn_sra_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:47:00 [insn_srai_ch0] base: finished (returncode=0) SBY 16:47:00 [insn_srai_ch0] smt2: starting process "cd insn_srai_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:47:00 [insn_sltu_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:00 [insn_sra_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:47:00 [insn_srl_ch0] base: finished (returncode=0) SBY 16:47:00 [insn_srl_ch0] smt2: starting process "cd insn_srl_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:47:00 [insn_srai_ch0] smt2: finished (returncode=0) SBY 16:47:00 [insn_srai_ch0] engine_0: starting process "cd insn_srai_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:47:00 [insn_sltu_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:00 [insn_sra_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:47:00 [insn_srai_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:47:00 [insn_srl_ch0] smt2: finished (returncode=0) SBY 16:47:00 [insn_srl_ch0] engine_0: starting process "cd insn_srl_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:47:00 [insn_sltu_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:00 [insn_sra_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:47:00 [insn_srl_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:47:00 [insn_srai_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:47:00 [insn_sltu_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:00 [insn_sra_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:47:00 [insn_srai_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:47:00 [insn_srl_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:47:00 [insn_sra_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:47:00 [insn_srai_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:47:00 [insn_srl_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:47:00 [insn_sra_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:00 [insn_srai_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:47:00 [insn_srl_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:47:00 [insn_sra_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:01 [insn_srai_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:47:01 [insn_srl_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:47:01 [insn_sra_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:01 [insn_srai_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:47:01 [insn_srl_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:47:01 [insn_sra_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:01 [insn_srai_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:47:01 [insn_srl_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:47:01 [insn_sb_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:47:01 [insn_srai_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:47:01 [insn_srl_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:47:01 [insn_srai_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:47:01 [insn_srl_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:47:01 [insn_srai_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:47:01 [insn_srl_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:47:01 [insn_srai_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:47:01 [insn_srl_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:47:02 [insn_srai_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:47:02 [insn_srl_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:47:02 [insn_srl_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:47:02 [insn_srai_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:47:02 [insn_srl_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:47:02 [insn_srai_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:47:02 [insn_srai_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:47:02 [insn_srl_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:47:02 [insn_srai_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:47:02 [insn_srl_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:47:02 [insn_srai_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:47:02 [insn_srl_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:47:02 [insn_srl_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:47:02 [insn_srai_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:03 [insn_srai_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:03 [insn_srl_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:03 [insn_srai_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:03 [insn_srl_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:03 [insn_sh_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:47:03 [insn_srai_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:03 [insn_srl_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:03 [insn_srl_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:04 [insn_or_ch0] engine_0: ## 0:01:38 Status: passed SBY 16:47:04 [insn_or_ch0] engine_0: finished (returncode=0) SBY 16:47:04 [insn_or_ch0] engine_0: Status returned by engine: pass SBY 16:47:04 [insn_or_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:44 (104) SBY 16:47:04 [insn_or_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:43 (103) SBY 16:47:04 [insn_or_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:47:04 [insn_or_ch0] DONE (PASS, rc=0) sby insn_srli_ch0.sby SBY 16:47:04 [insn_srli_ch0] Writing 'insn_srli_ch0/src/defines.sv'. SBY 16:47:04 [insn_srli_ch0] Writing 'insn_srli_ch0/src/insn_srli_ch0.sv'. SBY 16:47:04 [insn_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_srli_ch0/src/rvfi_macros.vh'. SBY 16:47:04 [insn_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_srli_ch0/src/rvfi_channel.sv'. SBY 16:47:04 [insn_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_srli_ch0/src/rvfi_testbench.sv'. SBY 16:47:04 [insn_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_srli_ch0/src/rvfi_insn_check.sv'. SBY 16:47:04 [insn_srli_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_srli.v' to 'insn_srli_ch0/src/insn_srli.v'. SBY 16:47:04 [insn_srli_ch0] engine_0: smtbmc --nopresat boolector SBY 16:47:04 [insn_srli_ch0] base: starting process "cd insn_srli_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:47:05 [insn_lbu_ch0] engine_0: ## 0:02:59 Status: passed SBY 16:47:05 [insn_lbu_ch0] engine_0: finished (returncode=0) SBY 16:47:05 [insn_lbu_ch0] engine_0: Status returned by engine: pass SBY 16:47:05 [insn_lbu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:03:05 (185) SBY 16:47:05 [insn_lbu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:03:05 (185) SBY 16:47:05 [insn_lbu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:47:05 [insn_lbu_ch0] DONE (PASS, rc=0) sby insn_sub_ch0.sby SBY 16:47:06 [insn_sub_ch0] Writing 'insn_sub_ch0/src/defines.sv'. SBY 16:47:06 [insn_sub_ch0] Writing 'insn_sub_ch0/src/insn_sub_ch0.sv'. SBY 16:47:06 [insn_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_sub_ch0/src/rvfi_macros.vh'. SBY 16:47:06 [insn_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_sub_ch0/src/rvfi_channel.sv'. SBY 16:47:06 [insn_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_sub_ch0/src/rvfi_testbench.sv'. SBY 16:47:06 [insn_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_sub_ch0/src/rvfi_insn_check.sv'. SBY 16:47:06 [insn_sub_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_sub.v' to 'insn_sub_ch0/src/insn_sub.v'. SBY 16:47:06 [insn_sub_ch0] engine_0: smtbmc --nopresat boolector SBY 16:47:06 [insn_sub_ch0] base: starting process "cd insn_sub_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:47:09 [insn_lb_ch0] engine_0: ## 0:03:11 Status: passed SBY 16:47:09 [insn_lb_ch0] engine_0: finished (returncode=0) SBY 16:47:09 [insn_lb_ch0] engine_0: Status returned by engine: pass SBY 16:47:09 [insn_lb_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:03:17 (197) SBY 16:47:09 [insn_lb_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:03:17 (197) SBY 16:47:09 [insn_lb_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:47:09 [insn_lb_ch0] DONE (PASS, rc=0) sby insn_sw_ch0.sby SBY 16:47:09 [insn_sw_ch0] Writing 'insn_sw_ch0/src/defines.sv'. SBY 16:47:09 [insn_sw_ch0] Writing 'insn_sw_ch0/src/insn_sw_ch0.sv'. SBY 16:47:09 [insn_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_sw_ch0/src/rvfi_macros.vh'. SBY 16:47:09 [insn_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_sw_ch0/src/rvfi_channel.sv'. SBY 16:47:09 [insn_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_sw_ch0/src/rvfi_testbench.sv'. SBY 16:47:09 [insn_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_sw_ch0/src/rvfi_insn_check.sv'. SBY 16:47:09 [insn_sw_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_sw.v' to 'insn_sw_ch0/src/insn_sw.v'. SBY 16:47:09 [insn_sw_ch0] engine_0: smtbmc --nopresat boolector SBY 16:47:09 [insn_sw_ch0] base: starting process "cd insn_sw_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:47:09 [insn_srli_ch0] base: finished (returncode=0) SBY 16:47:09 [insn_srli_ch0] smt2: starting process "cd insn_srli_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:47:10 [insn_srli_ch0] smt2: finished (returncode=0) SBY 16:47:10 [insn_srli_ch0] engine_0: starting process "cd insn_srli_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:47:10 [insn_srli_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:47:10 [insn_srli_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:47:10 [insn_srli_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:47:10 [insn_srli_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:47:10 [insn_srli_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:47:10 [insn_srli_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:47:11 [insn_srli_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:47:11 [insn_srli_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:47:11 [insn_srli_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:47:11 [insn_srli_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:47:11 [insn_srli_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:47:11 [insn_sub_ch0] base: finished (returncode=0) SBY 16:47:11 [insn_sub_ch0] smt2: starting process "cd insn_sub_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:47:11 [insn_srli_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:47:11 [insn_sub_ch0] smt2: finished (returncode=0) SBY 16:47:11 [insn_sub_ch0] engine_0: starting process "cd insn_sub_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:47:11 [insn_srli_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:47:11 [insn_sub_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:47:12 [insn_srli_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:47:12 [insn_sub_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:47:12 [insn_srli_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:47:12 [insn_sub_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:47:12 [insn_srli_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:47:12 [insn_sub_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:47:12 [insn_srli_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:47:12 [insn_sub_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:47:12 [insn_lw_ch0] engine_0: ## 0:02:43 Status: passed SBY 16:47:12 [insn_srli_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:47:12 [insn_lw_ch0] engine_0: finished (returncode=0) SBY 16:47:12 [insn_lw_ch0] engine_0: Status returned by engine: pass SBY 16:47:12 [insn_lw_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:49 (169) SBY 16:47:12 [insn_lw_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:49 (169) SBY 16:47:12 [insn_lw_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:47:12 [insn_lw_ch0] DONE (PASS, rc=0) sby insn_xor_ch0.sby SBY 16:47:12 [insn_sub_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:47:12 [insn_xor_ch0] Writing 'insn_xor_ch0/src/defines.sv'. SBY 16:47:12 [insn_xor_ch0] Writing 'insn_xor_ch0/src/insn_xor_ch0.sv'. SBY 16:47:12 [insn_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_xor_ch0/src/rvfi_macros.vh'. SBY 16:47:12 [insn_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_xor_ch0/src/rvfi_channel.sv'. SBY 16:47:12 [insn_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_xor_ch0/src/rvfi_testbench.sv'. SBY 16:47:12 [insn_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_xor_ch0/src/rvfi_insn_check.sv'. SBY 16:47:12 [insn_xor_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_xor.v' to 'insn_xor_ch0/src/insn_xor.v'. SBY 16:47:12 [insn_xor_ch0] engine_0: smtbmc --nopresat boolector SBY 16:47:12 [insn_xor_ch0] base: starting process "cd insn_xor_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:47:12 [insn_srli_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:12 [insn_sub_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:47:12 [insn_srli_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:12 [insn_sub_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:47:13 [insn_srli_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:13 [insn_sub_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:47:13 [insn_srli_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:13 [insn_sub_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:47:13 [insn_sub_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:47:13 [insn_sub_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:47:13 [insn_sub_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:47:13 [insn_sub_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:47:14 [insn_sub_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:47:14 [insn_sub_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:47:14 [insn_sub_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:47:14 [insn_sub_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:47:14 [insn_sub_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:14 [insn_sub_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:14 [insn_sub_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:15 [insn_sw_ch0] base: finished (returncode=0) SBY 16:47:15 [insn_sw_ch0] smt2: starting process "cd insn_sw_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:47:15 [insn_sub_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:15 [insn_sw_ch0] smt2: finished (returncode=0) SBY 16:47:15 [insn_sw_ch0] engine_0: starting process "cd insn_sw_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:47:15 [insn_sw_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:47:15 [insn_sw_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:47:15 [insn_sw_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:47:15 [insn_sw_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:47:15 [insn_sw_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:47:16 [insn_sw_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:47:16 [insn_sw_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:47:16 [insn_sw_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:47:16 [insn_sw_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:47:16 [insn_sw_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:47:16 [insn_sw_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:47:16 [insn_sw_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:47:17 [insn_sw_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:47:17 [insn_sw_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:47:17 [insn_sw_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:47:17 [insn_sw_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:47:17 [insn_sw_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:47:17 [insn_sw_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:47:17 [insn_sw_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:18 [insn_sw_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:18 [insn_sw_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:18 [insn_sw_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:18 [insn_xor_ch0] base: finished (returncode=0) SBY 16:47:18 [insn_xor_ch0] smt2: starting process "cd insn_xor_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:47:18 [insn_xor_ch0] smt2: finished (returncode=0) SBY 16:47:18 [insn_xor_ch0] engine_0: starting process "cd insn_xor_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:47:18 [insn_xor_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:47:18 [insn_xor_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:47:18 [insn_xor_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:47:19 [insn_xor_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:47:19 [insn_xor_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:47:19 [insn_xor_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:47:19 [insn_xor_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:47:19 [insn_xor_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:47:19 [insn_xor_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:47:19 [insn_xor_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:47:20 [insn_xor_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:47:20 [insn_xor_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:47:20 [insn_xor_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:47:20 [insn_xor_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:47:20 [insn_xor_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:47:20 [insn_xor_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:47:20 [insn_sll_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:47:20 [insn_xor_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:47:21 [insn_xor_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:47:21 [insn_xor_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:21 [insn_xor_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:21 [insn_xor_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:21 [insn_xor_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:31 [insn_slt_ch0] engine_0: ## 0:00:54 Status: passed SBY 16:47:31 [insn_slt_ch0] engine_0: finished (returncode=0) SBY 16:47:31 [insn_slt_ch0] engine_0: Status returned by engine: pass SBY 16:47:31 [insn_slt_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:59 (59) SBY 16:47:31 [insn_slt_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:59 (59) SBY 16:47:31 [insn_slt_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:47:31 [insn_slt_ch0] DONE (PASS, rc=0) sby insn_xori_ch0.sby SBY 16:47:31 [insn_xori_ch0] Writing 'insn_xori_ch0/src/defines.sv'. SBY 16:47:31 [insn_xori_ch0] Writing 'insn_xori_ch0/src/insn_xori_ch0.sv'. SBY 16:47:31 [insn_xori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh' to 'insn_xori_ch0/src/rvfi_macros.vh'. SBY 16:47:31 [insn_xori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv' to 'insn_xori_ch0/src/rvfi_channel.sv'. SBY 16:47:31 [insn_xori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv' to 'insn_xori_ch0/src/rvfi_testbench.sv'. SBY 16:47:31 [insn_xori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../checks/rvfi_insn_check.sv' to 'insn_xori_ch0/src/rvfi_insn_check.sv'. SBY 16:47:31 [insn_xori_ch0] Copy '/home/dsleung/Desktop/riscv-formal/cores/picorv32/../../insns/insn_xori.v' to 'insn_xori_ch0/src/insn_xori.v'. SBY 16:47:31 [insn_xori_ch0] engine_0: smtbmc --nopresat boolector SBY 16:47:31 [insn_xori_ch0] base: starting process "cd insn_xori_ch0/src; yosys -ql ../model/design.log ../model/design.ys" SBY 16:47:33 [insn_slli_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:47:37 [insn_xori_ch0] base: finished (returncode=0) SBY 16:47:37 [insn_xori_ch0] smt2: starting process "cd insn_xori_ch0/model; yosys -ql design_smt2.log design_smt2.ys" SBY 16:47:37 [insn_xori_ch0] smt2: finished (returncode=0) SBY 16:47:37 [insn_xori_ch0] engine_0: starting process "cd insn_xori_ch0; yosys-smtbmc -s boolector --unroll --noprogress -t 20:21 --append 0 --dump-vcd engine_0/trace.vcd --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" SBY 16:47:37 [insn_xori_ch0] engine_0: ## 0:00:00 Solver: boolector SBY 16:47:37 [insn_xori_ch0] engine_0: ## 0:00:00 Skipping step 0.. SBY 16:47:38 [insn_xori_ch0] engine_0: ## 0:00:00 Skipping step 1.. SBY 16:47:38 [insn_xori_ch0] engine_0: ## 0:00:00 Skipping step 2.. SBY 16:47:38 [insn_xori_ch0] engine_0: ## 0:00:00 Skipping step 3.. SBY 16:47:38 [insn_xori_ch0] engine_0: ## 0:00:00 Skipping step 4.. SBY 16:47:38 [insn_xori_ch0] engine_0: ## 0:00:00 Skipping step 5.. SBY 16:47:38 [insn_xori_ch0] engine_0: ## 0:00:01 Skipping step 6.. SBY 16:47:38 [insn_xori_ch0] engine_0: ## 0:00:01 Skipping step 7.. SBY 16:47:39 [insn_xori_ch0] engine_0: ## 0:00:01 Skipping step 8.. SBY 16:47:39 [insn_xori_ch0] engine_0: ## 0:00:01 Skipping step 9.. SBY 16:47:39 [insn_xori_ch0] engine_0: ## 0:00:01 Skipping step 10.. SBY 16:47:39 [insn_xori_ch0] engine_0: ## 0:00:01 Skipping step 11.. SBY 16:47:39 [insn_xori_ch0] engine_0: ## 0:00:01 Skipping step 12.. SBY 16:47:39 [insn_xori_ch0] engine_0: ## 0:00:02 Skipping step 13.. SBY 16:47:39 [insn_xori_ch0] engine_0: ## 0:00:02 Skipping step 14.. SBY 16:47:40 [insn_xori_ch0] engine_0: ## 0:00:02 Skipping step 15.. SBY 16:47:40 [insn_xori_ch0] engine_0: ## 0:00:02 Skipping step 16.. SBY 16:47:40 [insn_xori_ch0] engine_0: ## 0:00:02 Skipping step 17.. SBY 16:47:40 [insn_xori_ch0] engine_0: ## 0:00:02 Skipping step 18.. SBY 16:47:40 [insn_xori_ch0] engine_0: ## 0:00:02 Skipping step 19.. SBY 16:47:40 [insn_xori_ch0] engine_0: ## 0:00:03 Checking assertions in step 20.. SBY 16:47:43 [insn_slti_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:47:52 [insn_sltu_ch0] engine_0: ## 0:00:55 Status: passed SBY 16:47:52 [insn_sltu_ch0] engine_0: finished (returncode=0) SBY 16:47:52 [insn_sltu_ch0] engine_0: Status returned by engine: pass SBY 16:47:52 [insn_sltu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:00 (60) SBY 16:47:52 [insn_sltu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:00 (60) SBY 16:47:52 [insn_sltu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:47:52 [insn_sltu_ch0] DONE (PASS, rc=0) SBY 16:47:52 [insn_slti_ch0] engine_0: ## 0:01:13 Status: passed SBY 16:47:52 [insn_slti_ch0] engine_0: finished (returncode=0) SBY 16:47:52 [insn_slti_ch0] engine_0: Status returned by engine: pass SBY 16:47:52 [insn_slti_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:18 (78) SBY 16:47:52 [insn_slti_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:18 (78) SBY 16:47:52 [insn_slti_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:47:52 [insn_slti_ch0] DONE (PASS, rc=0) SBY 16:47:55 [insn_sltiu_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:01 [insn_sra_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:03 [insn_srai_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:03 [insn_srl_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:04 [insn_slli_ch0] engine_0: ## 0:01:33 Status: passed SBY 16:48:04 [insn_slli_ch0] engine_0: finished (returncode=0) SBY 16:48:04 [insn_slli_ch0] engine_0: Status returned by engine: pass SBY 16:48:04 [insn_slli_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:39 (99) SBY 16:48:04 [insn_slli_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:39 (99) SBY 16:48:04 [insn_slli_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:04 [insn_slli_ch0] DONE (PASS, rc=0) SBY 16:48:08 [insn_sltiu_ch0] engine_0: ## 0:01:16 Status: passed SBY 16:48:08 [insn_sltiu_ch0] engine_0: finished (returncode=0) SBY 16:48:08 [insn_sltiu_ch0] engine_0: Status returned by engine: pass SBY 16:48:08 [insn_sltiu_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:22 (82) SBY 16:48:08 [insn_sltiu_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:22 (82) SBY 16:48:08 [insn_sltiu_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:08 [insn_sltiu_ch0] DONE (PASS, rc=0) SBY 16:48:13 [insn_srli_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:15 [insn_sub_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:18 [insn_sw_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:21 [insn_xor_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:30 [insn_sra_ch0] engine_0: ## 0:01:32 Status: passed SBY 16:48:30 [insn_sra_ch0] engine_0: finished (returncode=0) SBY 16:48:30 [insn_sra_ch0] engine_0: Status returned by engine: pass SBY 16:48:30 [insn_sra_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:38 (98) SBY 16:48:30 [insn_sra_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:37 (97) SBY 16:48:30 [insn_sra_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:30 [insn_sra_ch0] DONE (PASS, rc=0) SBY 16:48:34 [insn_sll_ch0] engine_0: ## 0:02:16 Status: passed SBY 16:48:34 [insn_sll_ch0] engine_0: finished (returncode=0) SBY 16:48:34 [insn_sll_ch0] engine_0: Status returned by engine: pass SBY 16:48:34 [insn_sll_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:48:34 [insn_sll_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:22 (142) SBY 16:48:34 [insn_sll_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:34 [insn_sll_ch0] DONE (PASS, rc=0) SBY 16:48:39 [insn_srai_ch0] engine_0: ## 0:01:38 Status: passed SBY 16:48:39 [insn_srai_ch0] engine_0: finished (returncode=0) SBY 16:48:39 [insn_srai_ch0] engine_0: Status returned by engine: pass SBY 16:48:39 [insn_srai_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:44 (104) SBY 16:48:39 [insn_srai_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:44 (104) SBY 16:48:39 [insn_srai_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:39 [insn_srai_ch0] DONE (PASS, rc=0) SBY 16:48:41 [insn_xori_ch0] engine_0: ## 0:01:03 waiting for solver (1 minute) SBY 16:48:46 [insn_srli_ch0] engine_0: ## 0:01:36 Status: passed SBY 16:48:46 [insn_srli_ch0] engine_0: finished (returncode=0) SBY 16:48:46 [insn_srli_ch0] engine_0: Status returned by engine: pass SBY 16:48:46 [insn_srli_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:42 (102) SBY 16:48:46 [insn_srli_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:42 (102) SBY 16:48:46 [insn_srli_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:46 [insn_srli_ch0] DONE (PASS, rc=0) SBY 16:48:47 [insn_xori_ch0] engine_0: ## 0:01:09 Status: passed SBY 16:48:47 [insn_xori_ch0] engine_0: finished (returncode=0) SBY 16:48:47 [insn_xori_ch0] engine_0: Status returned by engine: pass SBY 16:48:47 [insn_xori_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:15 (75) SBY 16:48:47 [insn_xori_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:15 (75) SBY 16:48:47 [insn_xori_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:47 [insn_xori_ch0] DONE (PASS, rc=0) SBY 16:48:47 [insn_xor_ch0] engine_0: ## 0:01:28 Status: passed SBY 16:48:47 [insn_xor_ch0] engine_0: finished (returncode=0) SBY 16:48:47 [insn_xor_ch0] engine_0: Status returned by engine: pass SBY 16:48:47 [insn_xor_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:34 (94) SBY 16:48:47 [insn_xor_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:34 (94) SBY 16:48:47 [insn_xor_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:47 [insn_xor_ch0] DONE (PASS, rc=0) SBY 16:48:49 [insn_srl_ch0] engine_0: ## 0:01:49 Status: passed SBY 16:48:49 [insn_srl_ch0] engine_0: finished (returncode=0) SBY 16:48:49 [insn_srl_ch0] engine_0: Status returned by engine: pass SBY 16:48:49 [insn_srl_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:01:54 (114) SBY 16:48:49 [insn_srl_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:01:54 (114) SBY 16:48:49 [insn_srl_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:49 [insn_srl_ch0] DONE (PASS, rc=0) SBY 16:48:54 [insn_sh_ch0] engine_0: ## 0:02:54 Status: passed SBY 16:48:54 [insn_sh_ch0] engine_0: finished (returncode=0) SBY 16:48:54 [insn_sh_ch0] engine_0: Status returned by engine: pass SBY 16:48:54 [insn_sh_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:03:00 (180) SBY 16:48:54 [insn_sh_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:03:00 (180) SBY 16:48:54 [insn_sh_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:54 [insn_sh_ch0] DONE (PASS, rc=0) SBY 16:48:58 [insn_sb_ch0] engine_0: ## 0:03:00 Status: passed SBY 16:48:58 [insn_sb_ch0] engine_0: finished (returncode=0) SBY 16:48:58 [insn_sb_ch0] engine_0: Status returned by engine: pass SBY 16:48:58 [insn_sb_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:03:06 (186) SBY 16:48:58 [insn_sb_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:03:06 (186) SBY 16:48:58 [insn_sb_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:48:58 [insn_sb_ch0] DONE (PASS, rc=0) SBY 16:49:08 [reg_ch0] engine_0: ## 0:10:04 waiting for solver (10 minutes) SBY 16:49:19 [insn_sub_ch0] engine_0: ## 0:02:07 Status: passed SBY 16:49:19 [insn_sub_ch0] engine_0: finished (returncode=0) SBY 16:49:19 [insn_sub_ch0] engine_0: Status returned by engine: pass SBY 16:49:19 [insn_sub_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:13 (133) SBY 16:49:19 [insn_sub_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:13 (133) SBY 16:49:19 [insn_sub_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:49:19 [insn_sub_ch0] DONE (PASS, rc=0) SBY 16:49:30 [insn_sw_ch0] engine_0: ## 0:02:15 Status: passed SBY 16:49:30 [insn_sw_ch0] engine_0: finished (returncode=0) SBY 16:49:30 [insn_sw_ch0] engine_0: Status returned by engine: pass SBY 16:49:30 [insn_sw_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:02:21 (141) SBY 16:49:30 [insn_sw_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:02:21 (141) SBY 16:49:30 [insn_sw_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 16:49:30 [insn_sw_ch0] DONE (PASS, rc=0) SBY 16:54:08 [reg_ch0] engine_0: ## 0:15:04 waiting for solver (15 minutes) SBY 17:09:08 [reg_ch0] engine_0: ## 0:30:04 waiting for solver (30 minutes) SBY 17:23:52 [reg_ch0] engine_0: ## 0:44:47 Status: passed SBY 17:23:52 [reg_ch0] engine_0: finished (returncode=0) SBY 17:23:52 [reg_ch0] engine_0: Status returned by engine: pass SBY 17:23:52 [reg_ch0] summary: Elapsed clock time [H:MM:SS (secs)]: 0:44:51 (2691) SBY 17:23:52 [reg_ch0] summary: Elapsed process time [H:MM:SS (secs)]: 0:44:51 (2691) SBY 17:23:52 [reg_ch0] summary: engine_0 (smtbmc --nopresat boolector) returned pass SBY 17:23:52 [reg_ch0] DONE (PASS, rc=0) make: Leaving directory '/home/dsleung/Desktop/riscv-formal/cores/picorv32/checks'